624 lines
18 KiB
C
624 lines
18 KiB
C
/* $NetBSD: esp.c,v 1.2 1998/07/07 03:05:02 eeh Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy
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* Copyright (c) 1995 Paul Kranenburg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sparc64/dev/sbusvar.h>
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#include <sparc64/dev/dmareg.h>
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#include <sparc64/dev/dmavar.h>
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#include <sparc64/dev/espvar.h>
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void espattach_sbus __P((struct device *, struct device *, void *));
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void espattach_obio __P((struct device *, struct device *, void *));
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void espattach_dma __P((struct device *, struct device *, void *));
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int espmatch_sbus __P((struct device *, struct cfdata *, void *));
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int espmatch_obio __P((struct device *, struct cfdata *, void *));
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void espattach __P((struct esp_softc *));
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/* Linkup to the rest of the kernel */
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struct cfattach esp_sbus_ca = {
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sizeof(struct esp_softc), espmatch_sbus, espattach_sbus
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};
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch_sbus, espattach_dma
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};
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struct cfattach fas_ca = {
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sizeof(struct esp_softc), espmatch_sbus, espattach_sbus
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};
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struct cfattach esp_obio_ca = {
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sizeof(struct esp_softc), espmatch_obio, espattach_obio
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};
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struct scsipi_adapter esp_switch = {
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ncr53c9x_scsi_cmd,
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minphys, /* no max at this level; handled by DMA code */
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NULL,
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NULL,
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};
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struct scsipi_device esp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_dma_isintr __P((struct ncr53c9x_softc *));
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void esp_dma_reset __P((struct ncr53c9x_softc *));
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int esp_dma_intr __P((struct ncr53c9x_softc *));
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int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_dma_go __P((struct ncr53c9x_softc *));
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void esp_dma_stop __P((struct ncr53c9x_softc *));
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int esp_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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int
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espmatch_sbus(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct sbus_attach_args *sa = aux;
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return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
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}
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int
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espmatch_obio(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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union obio_attach_args *uoba = aux;
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struct obio4_attach_args *oba;
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if (uoba->uoba_isobio4 == 0)
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return (0);
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oba = &uoba->uoba_oba4;
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return (bus_space_probe(oba->oba_bustag, 0,
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oba->oba_paddr,
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1, /* probe size */
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0, /* offset */
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0, /* flags */
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NULL, NULL));
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}
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void
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espattach_sbus(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct sbus_attach_args *sa = aux;
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esc->sc_bustag = sa->sa_bustag;
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esc->sc_dmatag = sa->sa_dmatag;
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sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7);
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sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1);
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if (sc->sc_freq < 0)
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sc->sc_freq = ((struct sbus_softc *)
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sc->sc_dev.dv_parent)->sc_clockfreq;
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/*
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* Find the DMA by poking around the dma device structures
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*
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* What happens here is that if the dma driver has not been
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* configured, then this returns a NULL pointer. Then when the
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* dma actually gets configured, it does the opposing test, and
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* if the sc->sc_esp field in it's softc is NULL, then tries to
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* find the matching esp driver.
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*/
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esc->sc_dma = (struct dma_softc *)getdevunit("dma", sc->sc_dev.dv_unit);
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/*
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* and a back pointer to us, for DMA
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*/
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if (esc->sc_dma)
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esc->sc_dma->sc_esp = esc;
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else {
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/*
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* FAS chips have the DMA in the fas node. The first set
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* of "reg" is the DMA controller, the second set is the FAS366
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* itself. Need to deal w/this somehow.
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*/
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printf("\n");
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panic("espattach: no dma found");
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}
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/*
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* Map my registers in, if they aren't already in virtual
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* address space.
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*/
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if (sa->sa_promvaddr)
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esc->sc_reg = (volatile u_char *) sa->sa_promvaddr;
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else {
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bus_space_handle_t bh;
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset,
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sa->sa_size,
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BUS_SPACE_MAP_LINEAR,
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0, &bh) != 0) {
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printf("%s @ sbus: cannot map registers\n",
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self->dv_xname);
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return;
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}
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esc->sc_reg = (volatile u_char *)bh;
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}
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esc->sc_pri = sa->sa_pri;
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/* add me to the sbus structures */
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esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
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sbus_establish(&esc->sc_sd, &sc->sc_dev);
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if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 &&
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SAME_ESP(sc, sa->sa_bp, sa))
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bootpath_store(1, sa->sa_bp + 1);
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espattach(esc);
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}
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void
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espattach_dma(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct sbus_attach_args *sa = aux;
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esc->sc_bustag = sa->sa_bustag;
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esc->sc_dmatag = sa->sa_dmatag;
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sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7);
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sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1);
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esc->sc_dma = (struct dma_softc *)parent;
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esc->sc_dma->sc_esp = esc;
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/*
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* Map my registers in, if they aren't already in virtual
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* address space.
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*/
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if (sa->sa_promvaddr)
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esc->sc_reg = (volatile u_char *) sa->sa_promvaddr;
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else {
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bus_space_handle_t bh;
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if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
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sa->sa_offset,
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sa->sa_size,
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BUS_SPACE_MAP_LINEAR,
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0, &bh) != 0) {
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printf("%s @ dma: cannot map registers\n",
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self->dv_xname);
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return;
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}
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esc->sc_reg = (volatile u_char *)bh;
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}
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/* Establish interrupt handler */
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esc->sc_pri = sa->sa_pri;
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/* Assume SBus is grandparent */
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esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
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sbus_establish(&esc->sc_sd, parent);
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if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 &&
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SAME_ESP(sc, sa->sa_bp, sa))
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bootpath_store(1, sa->sa_bp + 1);
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espattach(esc);
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}
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void
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espattach_obio(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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union obio_attach_args *uoba = aux;
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struct obio4_attach_args *oba = &uoba->uoba_oba4;
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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bus_space_handle_t bh;
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esc->sc_bustag = oba->oba_bustag;
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esc->sc_dmatag = oba->oba_dmatag;
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sc->sc_id = 7;
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sc->sc_freq = 24000000;
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/*
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* Find the DMA by poking around the dma device structures
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*/
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esc->sc_dma = (struct dma_softc *)getdevunit("dma", sc->sc_dev.dv_unit);
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/*
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* and a back pointer to us, for DMA
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*/
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if (esc->sc_dma)
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esc->sc_dma->sc_esp = esc;
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else {
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printf("\n");
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panic("espattach: no dma found");
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}
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if (obio_bus_map(oba->oba_bustag, oba->oba_paddr,
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0, /* offset */
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16, /* size (of ncr53c9xreg) */
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BUS_SPACE_MAP_LINEAR,
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0, &bh) != 0) {
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printf("%s @ obio: cannot map registers\n", self->dv_xname);
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return;
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}
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esc->sc_reg = (volatile u_char *)bh;
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esc->sc_pri = oba->oba_pri;
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if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 &&
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oba->oba_bp->val[0] == -1 &&
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oba->oba_bp->val[1] == sc->sc_dev.dv_unit)
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bootpath_store(1, oba->oba_bp + 1);
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espattach(esc);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(esc)
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struct esp_softc *esc;
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{
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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void *icookie;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_glue;
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#if 0
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printf(" pri %d", esc->sc_pri);
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#endif
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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}
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|
}
|
|
|
|
/*
|
|
* XXX minsync and maxxfer _should_ be set up in MI code,
|
|
* XXX but it appears to have some dependency on what sort
|
|
* XXX of DMA we're hooked up to, etc.
|
|
*/
|
|
|
|
/*
|
|
* This is the value used to start sync negotiations
|
|
* Note that the NCR register "SYNCTP" is programmed
|
|
* in "clocks per byte", and has a minimum value of 4.
|
|
* The SCSI period used in negotiation is one-fourth
|
|
* of the time (in nanoseconds) needed to transfer one byte.
|
|
* Since the chip's clock is given in MHz, we have the following
|
|
* formula: 4 * period = (1000 / freq) * 4
|
|
*/
|
|
sc->sc_minsync = 1000 / sc->sc_freq;
|
|
|
|
/*
|
|
* Alas, we must now modify the value a bit, because it's
|
|
* only valid when can switch on FASTCLK and FASTSCSI bits
|
|
* in config register 3...
|
|
*/
|
|
switch (sc->sc_rev) {
|
|
case NCR_VARIANT_ESP100:
|
|
sc->sc_maxxfer = 64 * 1024;
|
|
sc->sc_minsync = 0; /* No synch on old chip? */
|
|
break;
|
|
|
|
case NCR_VARIANT_ESP100A:
|
|
sc->sc_maxxfer = 64 * 1024;
|
|
/* Min clocks/byte is 5 */
|
|
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
|
|
break;
|
|
|
|
case NCR_VARIANT_ESP200:
|
|
sc->sc_maxxfer = 16 * 1024 * 1024;
|
|
/* XXX - do actually set FAST* bits */
|
|
break;
|
|
}
|
|
|
|
/* Establish interrupt channel */
|
|
icookie = bus_intr_establish(esc->sc_bustag,
|
|
esc->sc_pri, 0,
|
|
(int(*)__P((void*)))ncr53c9x_intr, sc);
|
|
|
|
/* register interrupt stats */
|
|
evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);
|
|
|
|
/* Do the common parts of attachment. */
|
|
ncr53c9x_attach(sc, &esp_switch, &esp_dev);
|
|
|
|
/* Turn on target selection using the `dma' method */
|
|
ncr53c9x_dmaselect = 1;
|
|
|
|
bootpath_store(1, NULL);
|
|
}
|
|
|
|
/*
|
|
* Glue functions.
|
|
*/
|
|
|
|
u_char
|
|
esp_read_reg(sc, reg)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (esc->sc_reg[reg * 4]);
|
|
}
|
|
|
|
void
|
|
esp_write_reg(sc, reg, val)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
u_char val;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
u_char v = val;
|
|
|
|
esc->sc_reg[reg * 4] = v;
|
|
}
|
|
|
|
int
|
|
esp_dma_isintr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_ISINTR(esc->sc_dma));
|
|
}
|
|
|
|
void
|
|
esp_dma_reset(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_RESET(esc->sc_dma);
|
|
}
|
|
|
|
int
|
|
esp_dma_intr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_INTR(esc->sc_dma));
|
|
}
|
|
|
|
int
|
|
esp_dma_setup(sc, addr, len, datain, dmasize)
|
|
struct ncr53c9x_softc *sc;
|
|
caddr_t *addr;
|
|
size_t *len;
|
|
int datain;
|
|
size_t *dmasize;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize));
|
|
}
|
|
|
|
void
|
|
esp_dma_go(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_GO(esc->sc_dma);
|
|
}
|
|
|
|
void
|
|
esp_dma_stop(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMACSR(esc->sc_dma) &= ~D_EN_DMA;
|
|
}
|
|
|
|
int
|
|
esp_dma_isactive(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_ISACTIVE(esc->sc_dma));
|
|
}
|