537 lines
15 KiB
C
537 lines
15 KiB
C
/* $NetBSD: ite_rt.c,v 1.16 1996/04/23 22:53:12 veego Exp $ */
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/*
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* Copyright (c) 1993 Markus Wild
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* Copyright (c) 1993 Lutz Vieweg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Lutz Vieweg.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "grfrt.h"
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#if NGRFRT > 0
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/systm.h>
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#include <dev/cons.h>
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#include <machine/cpu.h>
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#include <amiga/amiga/device.h>
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#include <amiga/dev/itevar.h>
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#include <amiga/dev/grfioctl.h>
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#include <amiga/dev/grfvar.h>
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#include <amiga/dev/grf_rtreg.h>
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int retina_console = 1;
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void retina_cursor __P((struct ite_softc *,int));
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void retina_scroll __P((struct ite_softc *,int,int,int,int));
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void retina_deinit __P((struct ite_softc *));
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void retina_clear __P((struct ite_softc *,int,int,int,int));
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void retina_putc __P((struct ite_softc *,int,int,int,int));
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void retina_init __P((struct ite_softc *));
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#ifdef RETINA_SPEED_HACK
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static void screen_up __P((struct ite_softc *, int, int, int));
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static void screen_down __P((struct ite_softc *, int, int, int));
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#endif
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/*
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* this function is called from grf_rt to init the grf_softc->g_conpri
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* field each time a retina is attached.
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*/
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int
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grfrt_cnprobe()
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{
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static int done;
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int rv;
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if (retina_console && done == 0)
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rv = CN_INTERNAL;
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else
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rv = CN_NORMAL;
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done = 1;
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return(rv);
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}
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/*
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* init the required fields in the grf_softc struct for a
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* grf to function as an ite.
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*/
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void
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grfrt_iteinit(gp)
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struct grf_softc *gp;
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{
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gp->g_iteinit = retina_init;
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gp->g_itedeinit = retina_deinit;
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gp->g_iteclear = retina_clear;
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gp->g_iteputc = retina_putc;
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gp->g_itescroll = retina_scroll;
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gp->g_itecursor = retina_cursor;
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}
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void
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retina_init(ip)
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struct ite_softc *ip;
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{
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struct MonDef *md;
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ip->priv = ip->grf->g_data;
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md = (struct MonDef *) ip->priv;
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ip->cols = md->TX;
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ip->rows = md->TY;
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}
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void
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retina_cursor(ip, flag)
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struct ite_softc *ip;
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int flag;
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{
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volatile caddr_t ba = ip->grf->g_regkva;
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if (flag == ERASE_CURSOR)
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{
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/* disable cursor */
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WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20);
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}
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else
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{
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int pos = ip->curx + ip->cury * ip->cols;
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/* make sure to enable cursor */
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WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20);
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/* and position it */
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WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8));
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WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos);
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ip->cursorx = ip->curx;
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ip->cursory = ip->cury;
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}
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}
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#ifdef RETINA_SPEED_HACK
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static void
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screen_up(ip, top, bottom, lines)
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struct ite_softc *ip;
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int top;
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int bottom;
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int lines;
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{
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volatile caddr_t ba = ip->grf->g_regkva;
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volatile caddr_t fb = ip->grf->g_fbkva;
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const struct MonDef * md = (struct MonDef *) ip->priv;
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#ifdef BANKEDDEVPAGER
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int bank;
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#endif
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/* do some bounds-checking here.. */
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if (top >= bottom)
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return;
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if (top + lines >= bottom)
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{
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retina_clear (ip, top, 0, bottom - top, ip->cols);
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return;
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}
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#ifdef BANKEDDEVPAGER
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/* make sure to save/restore active bank (and if it's only
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for tests of the feature in text-mode..) */
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bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO)
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| (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8));
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#endif
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/* the trick here is to use a feature of the NCR chip. It can
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optimize data access in various read/write modes. One of
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the modes is able to read/write from/to different zones.
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Thus, by setting the read-offset to lineN, and the write-offset
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to line0, we just cause read/write cycles for all characters
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up to the last line, and have the chip transfer the data. The
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`addqb' are the cheapest way to cause read/write cycles (DONT
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use `tas' on the Amiga!), their results are completely ignored
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by the NCR chip, it just replicates what it just read. */
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/* write to primary, read from secondary */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
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(RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE,
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(RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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/* write to line TOP */
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long toploc = top * (md->TX / 16);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc));
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8)));
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}
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{
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/* read from line TOP + LINES */
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long fromloc = (top+lines) * (md->TX / 16);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ;
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
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}
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{
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caddr_t p = (caddr_t)fb;
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/* transfer all characters but LINES lines, unroll by 16 */
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short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
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do {
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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} while (x--);
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}
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/* reset to default values */
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE,
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(RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR,
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RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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/* read/write to primary on A0, secondary on B0 */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
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(RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40);
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/* fill the free lines with spaces */
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{ /* feed latches with value */
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unsigned short * f = (unsigned short *) fb;
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f += (1 + bottom - lines) * md->TX * 2;
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*f = 0x2010;
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}
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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unsigned long * p = (unsigned long *) fb;
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short x = (lines * (md->TX/16)) - 1;
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const unsigned long dummyval = 0;
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p += (1 + bottom - lines) * (md->TX/4);
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do {
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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} while (x--);
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}
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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#ifdef BANKEDDEVPAGER
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/* restore former bank */
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank);
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bank >>= 8;
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank);
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#endif
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};
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static void
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screen_down(ip, top, bottom, lines)
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struct ite_softc *ip;
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int top;
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int bottom;
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int lines;
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{
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volatile caddr_t ba = ip->grf->g_regkva;
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volatile caddr_t fb = ip->grf->g_fbkva;
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const struct MonDef * md = (struct MonDef *) ip->priv;
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#ifdef BANKEDDEVPAGER
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int bank;
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#endif
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/* do some bounds-checking here.. */
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if (top >= bottom)
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return;
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if (top + lines >= bottom)
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{
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retina_clear (ip, top, 0, bottom - top, ip->cols);
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return;
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}
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#ifdef BANKEDDEVPAGER
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/* make sure to save/restore active bank (and if it's only
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for tests of the feature in text-mode..) */
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bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO)
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| (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8));
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#endif
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/* see screen_up() for explanation of chip-tricks */
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/* write to primary, read from secondary */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
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(RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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/* write to line TOP + LINES */
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long toloc = (top + lines) * (md->TX / 16);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc));
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8)));
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}
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{
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/* read from line TOP */
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long fromloc = top * (md->TX / 16);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc));
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
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}
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{
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caddr_t p = (caddr_t)fb;
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short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
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p += (1 + bottom - (top + lines)) * md->TX;
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do {
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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} while (x--);
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}
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE,
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(RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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/* read/write to primary on A0, secondary on B0 */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
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(RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 );
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/* fill the free lines with spaces */
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{ /* feed latches with value */
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unsigned short * f = (unsigned short *) fb;
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f += top * md->TX * 2;
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*f = 0x2010;
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}
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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unsigned long * p = (unsigned long *) fb;
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short x = (lines * (md->TX/16)) - 1;
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const unsigned long dummyval = 0;
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p += top * (md->TX/4);
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do {
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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} while (x--);
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}
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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#ifdef BANKEDDEVPAGER
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/* restore former bank */
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank);
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bank >>= 8;
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank);
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#endif
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};
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#endif /* RETINA_SPEED_HACK */
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void
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retina_deinit(ip)
|
|
struct ite_softc *ip;
|
|
{
|
|
ip->flags &= ~ITE_INITED;
|
|
}
|
|
|
|
|
|
void
|
|
retina_putc(ip, c, dy, dx, mode)
|
|
struct ite_softc *ip;
|
|
int c;
|
|
int dy;
|
|
int dx;
|
|
int mode;
|
|
{
|
|
volatile caddr_t fb = ip->grf->g_fbkva;
|
|
register u_char attr;
|
|
|
|
attr = (mode & ATTR_INV) ? 0x21 : 0x10;
|
|
if (mode & ATTR_UL) attr = 0x01; /* ???????? */
|
|
if (mode & ATTR_BOLD) attr |= 0x08;
|
|
if (mode & ATTR_BLINK) attr |= 0x80;
|
|
|
|
fb += 4 * (dy * ip->cols + dx);
|
|
*fb++ = c; *fb = attr;
|
|
}
|
|
|
|
|
|
void
|
|
retina_clear(ip, sy, sx, h, w)
|
|
struct ite_softc *ip;
|
|
int sy;
|
|
int sx;
|
|
int h;
|
|
int w;
|
|
{
|
|
u_short * fb = (u_short *) ip->grf->g_fbkva;
|
|
short x;
|
|
const u_short fillval = 0x2010;
|
|
|
|
/* could probably be optimized just like the scrolling functions !! */
|
|
fb += 2 * (sy * ip->cols + sx);
|
|
while (h--)
|
|
{
|
|
for (x = 2 * (w - 1); x >= 0; x -= 2)
|
|
fb[x] = fillval;
|
|
fb += 2 * ip->cols;
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* RETINA_SPEED_HACK code seems to work on some boards and on others
|
|
* it causes text to smear horizontally
|
|
*/
|
|
void
|
|
retina_scroll(ip, sy, sx, count, dir)
|
|
struct ite_softc *ip;
|
|
int sy;
|
|
int sx;
|
|
int count;
|
|
int dir;
|
|
{
|
|
volatile caddr_t ba;
|
|
u_long *fb;
|
|
|
|
ba = ip->grf->g_regkva;
|
|
fb = (u_long *)ip->grf->g_fbkva;
|
|
|
|
retina_cursor(ip, ERASE_CURSOR);
|
|
|
|
if (dir == SCROLL_UP) {
|
|
#ifdef RETINA_SPEED_HACK
|
|
screen_up(ip, sy - count, ip->bottom_margin, count);
|
|
#else
|
|
bcopy(fb + sy * ip->cols, fb + (sy - count) * ip->cols,
|
|
4 * (ip->bottom_margin - sy + 1) * ip->cols);
|
|
retina_clear(ip, ip->bottom_margin + 1 - count, 0, count,
|
|
ip->cols);
|
|
#endif
|
|
} else if (dir == SCROLL_DOWN) {
|
|
#ifdef RETINA_SPEED_HACK
|
|
screen_down(ip, sy, ip->bottom_margin, count);
|
|
#else
|
|
bcopy(fb + sy * ip->cols, fb + (sy + count) * ip->cols,
|
|
4 * (ip->bottom_margin - sy - count + 1) * ip->cols);
|
|
retina_clear(ip, sy, 0, count, ip->cols);
|
|
#endif
|
|
} else if (dir == SCROLL_RIGHT) {
|
|
bcopy(fb + sx + sy * ip->cols, fb + sx + sy * ip->cols + count,
|
|
4 * (ip->cols - (sx + count)));
|
|
retina_clear(ip, sy, sx, 1, count);
|
|
} else {
|
|
bcopy(fb + sx + sy * ip->cols, fb + sx - count + sy * ip->cols,
|
|
4 * (ip->cols - sx));
|
|
retina_clear(ip, sy, ip->cols - count, 1, count);
|
|
}
|
|
#ifndef RETINA_SPEED_HACK
|
|
retina_cursor(ip, !ERASE_CURSOR);
|
|
#endif
|
|
}
|
|
|
|
#endif /* NGRFRT */
|