d974db0ada
This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
554 lines
15 KiB
C
554 lines
15 KiB
C
/* $NetBSD: wdc_obio.c,v 1.47 2007/10/17 19:55:20 garbled Exp $ */
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/*-
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* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Onno van der Linden.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.47 2007/10/17 19:55:20 garbled Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/pio.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcvar.h>
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#include <dev/ofw/openfirm.h>
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#include <macppc/dev/dbdma.h>
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#define WDC_REG_NPORTS 8
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#define WDC_AUXREG_OFFSET 0x16
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#define WDC_DEFAULT_PIO_IRQ 13 /* XXX */
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#define WDC_DEFAULT_DMA_IRQ 2 /* XXX */
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#define WDC_OPTIONS_DMA 0x01
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/*
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* XXX This code currently doesn't even try to allow 32-bit data port use.
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*/
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struct wdc_obio_softc {
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struct wdc_softc sc_wdcdev;
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struct ata_channel *sc_chanptr;
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struct ata_channel sc_channel;
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struct ata_queue sc_chqueue;
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struct wdc_regs sc_wdc_regs;
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bus_space_handle_t sc_dmaregh;
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dbdma_regmap_t *sc_dmareg;
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dbdma_command_t *sc_dmacmd;
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u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */
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void *sc_ih;
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};
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int wdc_obio_probe __P((struct device *, struct cfdata *, void *));
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void wdc_obio_attach __P((struct device *, struct device *, void *));
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int wdc_obio_detach __P((struct device *, int));
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int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int));
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void wdc_obio_dma_start __P((void *, int, int));
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int wdc_obio_dma_finish __P((void *, int, int, int));
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static void wdc_obio_select __P((struct ata_channel *, int));
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static void adjust_timing __P((struct ata_channel *));
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static void ata4_adjust_timing __P((struct ata_channel *));
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CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc),
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wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate);
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static const char *ata_names[] = {
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"heathrow-ata",
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"keylargo-ata",
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"ohare-ata",
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NULL
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};
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int
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wdc_obio_probe(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct confargs *ca = aux;
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/* XXX should not use name */
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if (strcmp(ca->ca_name, "ATA") == 0 ||
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strcmp(ca->ca_name, "ata") == 0 ||
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strcmp(ca->ca_name, "ata0") == 0 ||
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strcmp(ca->ca_name, "ide") == 0)
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return 1;
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if (of_compatible(ca->ca_node, ata_names) >= 0)
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return 1;
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return 0;
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}
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void
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wdc_obio_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct wdc_obio_softc *sc = (void *)self;
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struct wdc_regs *wdr;
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struct confargs *ca = aux;
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struct ata_channel *chp = &sc->sc_channel;
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int intr, i, type = IST_EDGE;
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int use_dma = 0;
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char path[80];
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if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
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WDC_OPTIONS_DMA) {
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if (ca->ca_nreg >= 16 || ca->ca_nintr == -1)
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use_dma = 1; /* XXX Don't work yet. */
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}
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if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) {
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intr = ca->ca_intr[0];
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printf(" irq %d", intr);
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if (ca->ca_nintr > 8) {
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type = ca->ca_intr[1] ? IST_LEVEL : IST_EDGE;
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}
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printf(", %s triggered", (type == IST_EDGE) ? "edge" : "level");
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} else if (ca->ca_nintr == -1) {
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intr = WDC_DEFAULT_PIO_IRQ;
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printf(" irq property not found; using %d", intr);
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} else {
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printf(": couldn't get irq property\n");
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return;
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}
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if (use_dma)
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printf(": DMA transfer");
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printf("\n");
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sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
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wdr->cmd_iot = wdr->ctl_iot = ca->ca_tag;
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if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[0],
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WDC_REG_NPORTS << 4, 0, &wdr->cmd_baseioh) ||
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bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) {
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printf("%s: couldn't map registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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return;
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}
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for (i = 0; i < WDC_NREG; i++) {
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4,
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i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
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bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
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WDC_REG_NPORTS << 4);
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printf("%s: couldn't subregion registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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return;
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}
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}
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#if 0
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = wdr->cmd_ioh;
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#endif
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sc->sc_ih = intr_establish(intr, type, IPL_BIO, wdcintr, chp);
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if (use_dma) {
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sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20);
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/*
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* XXX
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* we don't use ca->ca_reg[3] for size here because at least
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* on the PB3400c it says 0x200 for both IDE channels ( the
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* one on the mainboard and the other on the mediabay ) but
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* their start addresses are only 0x100 apart. Since those
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* DMA registers are always 0x100 or less we don't really
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* have to care though
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*/
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if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[2],
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0x100, BUS_SPACE_MAP_LINEAR, &sc->sc_dmaregh)) {
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aprint_error("%s: unable to map DMA registers (%08x)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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ca->ca_reg[2]);
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/* should unmap stuff here */
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return;
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}
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sc->sc_dmareg = bus_space_vaddr(wdr->cmd_iot, sc->sc_dmaregh);
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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if (strcmp(ca->ca_name, "ata-4") == 0) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_set_modes =
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ata4_adjust_timing;
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} else {
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sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
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}
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#ifdef notyet
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/* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */
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if (ohare) {
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 3;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 1;
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}
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#endif
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} else {
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/* all non-DMA controllers can use adjust_timing */
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sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
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sc->sc_chanptr = chp;
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sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = wdc_obio_dma_init;
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sc->sc_wdcdev.dma_start = wdc_obio_dma_start;
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sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish;
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chp->ch_channel = 0;
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chp->ch_atac = &sc->sc_wdcdev.sc_atac;
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chp->ch_queue = &sc->sc_chqueue;
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chp->ch_ndrive = 2;
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wdc_init_shadow_regs(chp);
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#define OHARE_FEATURE_REG 0xf3000038
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/* XXX Enable wdc1 by feature reg. */
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memset(path, 0, sizeof(path));
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OF_package_to_path(ca->ca_node, path, sizeof(path));
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if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) {
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u_int x;
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x = in32rb(OHARE_FEATURE_REG);
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x |= 8;
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out32rb(OHARE_FEATURE_REG, x);
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}
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wdcattach(chp);
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}
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/* Multiword DMA transfer timings */
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struct ide_timings {
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int cycle; /* minimum cycle time [ns] */
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int active; /* minimum command active time [ns] */
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};
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static struct ide_timings pio_timing[5] = {
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{ 600, 180 }, /* Mode 0 */
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{ 390, 150 }, /* 1 */
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{ 240, 105 }, /* 2 */
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{ 180, 90 }, /* 3 */
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{ 120, 75 } /* 4 */
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};
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static struct ide_timings dma_timing[3] = {
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{ 480, 240 }, /* Mode 0 */
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{ 165, 90 }, /* Mode 1 */
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{ 120, 75 } /* Mode 2 */
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};
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static struct ide_timings udma_timing[5] = {
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{120, 180}, /* Mode 0 */
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{ 90, 150}, /* Mode 1 */
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{ 60, 120}, /* Mode 2 */
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{ 45, 90}, /* Mode 3 */
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{ 30, 90} /* Mode 4 */
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};
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#define TIME_TO_TICK(time) howmany((time), 30)
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#define PIO_REC_OFFSET 4
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#define PIO_REC_MIN 1
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#define PIO_ACT_MIN 1
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#define DMA_REC_OFFSET 1
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#define DMA_REC_MIN 1
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#define DMA_ACT_MIN 1
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#define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */
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#define CONFIG_REG (0x200) /* IDE access timing register */
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void
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wdc_obio_select(chp, drive)
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struct ata_channel *chp;
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int drive;
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{
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struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
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bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh,
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CONFIG_REG, sc->sc_dmaconf[drive]);
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}
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void
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adjust_timing(chp)
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struct ata_channel *chp;
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{
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struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
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int drive;
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int min_cycle = 0, min_active = 0;
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int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
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for (drive = 0; drive < 2; drive++) {
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u_int conf = 0;
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struct ata_drive_datas *drvp;
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drvp = &chp->ch_drive[drive];
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/* set up pio mode timings */
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if (drvp->drive_flags & DRIVE) {
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int piomode = drvp->PIO_mode;
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min_cycle = pio_timing[piomode].cycle;
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min_active = pio_timing[piomode].active;
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cycle_tick = TIME_TO_TICK(min_cycle);
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act_tick = TIME_TO_TICK(min_active);
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if (act_tick < PIO_ACT_MIN)
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act_tick = PIO_ACT_MIN;
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inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
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if (inact_tick < PIO_REC_MIN)
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inact_tick = PIO_REC_MIN;
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/* mask: 0x000007ff */
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conf |= (inact_tick << 5) | act_tick;
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}
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/* Set up DMA mode timings */
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if (drvp->drive_flags & DRIVE_DMA) {
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int dmamode = drvp->DMA_mode;
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min_cycle = dma_timing[dmamode].cycle;
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min_active = dma_timing[dmamode].active;
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cycle_tick = TIME_TO_TICK(min_cycle);
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act_tick = TIME_TO_TICK(min_active);
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inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
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if (inact_tick < DMA_REC_MIN)
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inact_tick = DMA_REC_MIN;
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half_tick = 0; /* XXX */
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/* mask: 0xfffff800 */
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conf |=
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(half_tick << 21) |
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(inact_tick << 16) | (act_tick << 11);
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}
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#ifdef DEBUG
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if (conf) {
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printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n",
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drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick);
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}
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#endif
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sc->sc_dmaconf[drive] = conf;
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}
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sc->sc_wdcdev.select = 0;
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if (sc->sc_dmaconf[0]) {
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wdc_obio_select(chp,0);
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if (sc->sc_dmaconf[1] &&
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(sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) {
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sc->sc_wdcdev.select = wdc_obio_select;
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}
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} else if (sc->sc_dmaconf[1]) {
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wdc_obio_select(chp,1);
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}
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}
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void
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ata4_adjust_timing(chp)
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struct ata_channel *chp;
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{
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struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
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int drive;
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int min_cycle = 0, min_active = 0;
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int cycle_tick = 0, act_tick = 0, inact_tick = 0;
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for (drive = 0; drive < 2; drive++) {
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u_int conf = 0;
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struct ata_drive_datas *drvp;
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drvp = &chp->ch_drive[drive];
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/* set up pio mode timings */
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if (drvp->drive_flags & DRIVE) {
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int piomode = drvp->PIO_mode;
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min_cycle = pio_timing[piomode].cycle;
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min_active = pio_timing[piomode].active;
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cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
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act_tick = ATA4_TIME_TO_TICK(min_active);
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inact_tick = cycle_tick - act_tick;
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/* mask: 0x000003ff */
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conf |= (inact_tick << 5) | act_tick;
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}
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/* set up dma mode timings */
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if (drvp->drive_flags & DRIVE_DMA) {
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int dmamode = drvp->DMA_mode;
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min_cycle = dma_timing[dmamode].cycle;
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min_active = dma_timing[dmamode].active;
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cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
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act_tick = ATA4_TIME_TO_TICK(min_active);
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inact_tick = cycle_tick - act_tick;
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/* mask: 0x001ffc00 */
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conf |= (act_tick << 10) | (inact_tick << 15);
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}
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/* set up udma mode timings */
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if (drvp->drive_flags & DRIVE_UDMA) {
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int udmamode = drvp->UDMA_mode;
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min_cycle = udma_timing[udmamode].cycle;
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min_active = udma_timing[udmamode].active;
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act_tick = ATA4_TIME_TO_TICK(min_active);
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cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
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/* mask: 0x1ff00000 */
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conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000;
|
|
}
|
|
#ifdef DEBUG
|
|
if (conf) {
|
|
printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n",
|
|
drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick);
|
|
}
|
|
#endif
|
|
sc->sc_dmaconf[drive] = conf;
|
|
}
|
|
sc->sc_wdcdev.select = 0;
|
|
if (sc->sc_dmaconf[0]) {
|
|
wdc_obio_select(chp,0);
|
|
if (sc->sc_dmaconf[1] &&
|
|
(sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) {
|
|
sc->sc_wdcdev.select = wdc_obio_select;
|
|
}
|
|
} else if (sc->sc_dmaconf[1]) {
|
|
wdc_obio_select(chp,1);
|
|
}
|
|
}
|
|
|
|
int
|
|
wdc_obio_detach(self, flags)
|
|
struct device *self;
|
|
int flags;
|
|
{
|
|
struct wdc_obio_softc *sc = (void *)self;
|
|
int error;
|
|
|
|
if ((error = wdcdetach(self, flags)) != 0)
|
|
return error;
|
|
|
|
intr_disestablish(sc->sc_ih);
|
|
|
|
/* Unmap our i/o space. */
|
|
bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
|
|
sc->sc_wdcdev.regs->cmd_baseioh, WDC_REG_NPORTS << 4);
|
|
|
|
/* Unmap DMA registers. */
|
|
/* XXX unmapiodev(sc->sc_dmareg); */
|
|
/* XXX free(sc->sc_dmacmd); */
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags)
|
|
void *v;
|
|
void *databuf;
|
|
size_t datalen;
|
|
int flags;
|
|
{
|
|
struct wdc_obio_softc *sc = v;
|
|
vaddr_t va = (vaddr_t)databuf;
|
|
dbdma_command_t *cmdp;
|
|
u_int cmd, offset;
|
|
int read = flags & WDC_DMA_READ;
|
|
|
|
cmdp = sc->sc_dmacmd;
|
|
cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
|
|
|
|
offset = va & PGOFSET;
|
|
|
|
/* if va is not page-aligned, setup the first page */
|
|
if (offset != 0) {
|
|
int rest = PAGE_SIZE - offset; /* the rest of the page */
|
|
|
|
if (datalen > rest) { /* if continues to next page */
|
|
DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va),
|
|
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
|
|
DBDMA_BRANCH_NEVER);
|
|
datalen -= rest;
|
|
va += rest;
|
|
cmdp++;
|
|
}
|
|
}
|
|
|
|
/* now va is page-aligned */
|
|
while (datalen > PAGE_SIZE) {
|
|
DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va),
|
|
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
|
|
datalen -= PAGE_SIZE;
|
|
va += PAGE_SIZE;
|
|
cmdp++;
|
|
}
|
|
|
|
/* the last page (datalen <= PAGE_SIZE here) */
|
|
cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
|
|
DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va),
|
|
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
|
|
cmdp++;
|
|
|
|
DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
|
|
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
wdc_obio_dma_start(v, channel, drive)
|
|
void *v;
|
|
int channel, drive;
|
|
{
|
|
struct wdc_obio_softc *sc = v;
|
|
|
|
dbdma_start(sc->sc_dmareg, sc->sc_dmacmd);
|
|
}
|
|
|
|
int
|
|
wdc_obio_dma_finish(v, channel, drive, read)
|
|
void *v;
|
|
int channel, drive;
|
|
int read;
|
|
{
|
|
struct wdc_obio_softc *sc = v;
|
|
|
|
dbdma_stop(sc->sc_dmareg);
|
|
return 0;
|
|
}
|