168 lines
5.6 KiB
C
168 lines
5.6 KiB
C
/* $NetBSD: cpu.h,v 1.20 1995/12/21 05:02:10 mycroft Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1993 Adam Glass
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: cpu.h 1.16 91/03/25
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* from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
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* cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp
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*/
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#ifdef _KERNEL
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/*
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* Exported definitions unique to sun3/68k cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_swapin(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe. One the sun3, we use
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* what the hardware pushes on an interrupt (frame format 0).
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*/
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struct clockframe {
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u_short sr; /* sr at time of interrupt */
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u_long pc; /* pc at time of interrupt */
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u_short vo; /* vector offset (4-word frame) */
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};
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#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#if 0
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/* We would like to do it this way... */
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#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
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#else
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/* but until we start using PSL_M, we have to do this instead */
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#define CLKF_INTR(framep) (0) /* XXX */
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#endif
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extern int astpending; /* need to trap before returning to user mode */
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#define aston() (astpending++)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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extern int want_resched; /* resched() was called */
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#define need_resched() { want_resched++; aston(); }
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the sun3, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston())
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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/*
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* Software Interrupt Register (SIR)
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* The sun3 has a real software interrupt register set by
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* isr_soft_request() so this scheme just multiplexes four
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* software interrupt `sources' on the level one handler.
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*/
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union sun3sir {
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int sir_any;
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char sir_which[4];
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} sun3sir;
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#define SIR_NET 0
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#define SIR_CLOCK 1
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#define SIR_SPARE2 2
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#define SIR_SPARE3 3
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#define setsoftint() isr_soft_request(1)
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#define setsoftnet() (sun3sir.sir_which[SIR_NET] = 1, setsoftint())
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#define setsoftclock() (sun3sir.sir_which[SIR_CLOCK] = 1, setsoftint())
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_MAXID 2 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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}
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/* values for cpu_machine_id */
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#define CPU_ARCH_MASK 0xf0
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#define SUN3_ARCH 0x10
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#define SUN3_IMPL_MASK 0x0f
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#define SUN3_MACH_160 0x01
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#define SUN3_MACH_50 0x02
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#define SUN3_MACH_260 0x03
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#define SUN3_MACH_110 0x04
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#define SUN3_MACH_60 0x07
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#define SUN3_MACH_E 0x08
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extern unsigned char cpu_machine_id;
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_CONTROL 3 /* sun control space */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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#define IC_CLEAR (IC_CLR|IC_ENABLE)
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#endif /* _KERNEL */
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