247 lines
7.3 KiB
C
247 lines
7.3 KiB
C
/* $Id: njata_cardbus.c,v 1.13 2010/03/11 17:27:40 dyoung Exp $ */
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/*
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* Copyright (c) 2006 ITOH Yasufumi <itohy@NetBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: njata_cardbus.c,v 1.13 2010/03/11 17:27:40 dyoung Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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#include <dev/ic/ninjaata32reg.h>
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#include <dev/ic/ninjaata32var.h>
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#define NJATA32_CARDBUS_BASEADDR_IO PCI_BAR0
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#define NJATA32_CARDBUS_BASEADDR_MEM PCI_BAR1
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struct njata32_cardbus_softc {
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struct njata32_softc sc_njata32;
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/* CardBus-specific goo */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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pcitag_t sc_tag;
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bus_space_handle_t sc_regmaph;
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bus_size_t sc_regmap_size;
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};
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static const struct njata32_cardbus_product *njata_cardbus_lookup
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(const struct cardbus_attach_args *);
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static int njata_cardbus_match(device_t, cfdata_t, void *);
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static void njata_cardbus_attach(device_t, device_t, void *);
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static int njata_cardbus_detach(device_t, int);
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CFATTACH_DECL_NEW(njata_cardbus, sizeof(struct njata32_cardbus_softc),
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njata_cardbus_match, njata_cardbus_attach, njata_cardbus_detach, NULL);
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static const struct njata32_cardbus_product {
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pci_vendor_id_t p_vendor;
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pci_product_id_t p_product;
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uint8_t p_flags;
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#define NJATA32_FL_IOMAP_ONLY 1 /* registers are only in the I/O map */
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} njata32_cardbus_products[] = {
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{ PCI_VENDOR_IODATA, PCI_PRODUCT_IODATA_CBIDE2,
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0 },
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{ PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJATA32BI,
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0 },
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{ PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJATA32BI_KME,
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0 },
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{ PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NPATA32_CF32A,
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NJATA32_FL_IOMAP_ONLY },
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{ PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NPATA32_CF32A_BUFFALO,
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NJATA32_FL_IOMAP_ONLY },
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{ PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NPATA32_KME,
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NJATA32_FL_IOMAP_ONLY },
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{ PCI_VENDOR_INVALID, 0,
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0 }
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};
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static const struct njata32_cardbus_product *
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njata_cardbus_lookup(const struct cardbus_attach_args *ca)
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{
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const struct njata32_cardbus_product *p;
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for (p = njata32_cardbus_products;
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p->p_vendor != PCI_VENDOR_INVALID; p++) {
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if (PCI_VENDOR(ca->ca_id) == p->p_vendor &&
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PCI_PRODUCT(ca->ca_id) == p->p_product)
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return p;
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}
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return NULL;
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}
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static int
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njata_cardbus_match(device_t parent, cfdata_t match, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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if (njata_cardbus_lookup(ca))
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return 1;
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return 0;
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}
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static void
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njata_cardbus_attach(device_t parent, device_t self, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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struct njata32_cardbus_softc *csc = device_private(self);
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struct njata32_softc *sc = &csc->sc_njata32;
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const struct njata32_cardbus_product *prod;
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cardbus_devfunc_t ct = ca->ca_ct;
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pcireg_t reg;
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int csr;
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uint8_t latency = 0x20;
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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if ((prod = njata_cardbus_lookup(ca)) == NULL)
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panic("njata_cardbus_attach");
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aprint_normal(": Workbit NinjaATA-32 IDE controller\n");
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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/*
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* Map the device.
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*/
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csr = PCI_COMMAND_MASTER_ENABLE;
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/*
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* Map registers.
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* Try memory map first, and then try I/O.
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*/
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if ((prod->p_flags & NJATA32_FL_IOMAP_ONLY) == 0 &&
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Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
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PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&NJATA32_REGT(sc), &csc->sc_regmaph, NULL, &csc->sc_regmap_size)
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== 0) {
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if (bus_space_subregion(NJATA32_REGT(sc), csc->sc_regmaph,
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NJATA32_MEMOFFSET_REG, NJATA32_REGSIZE, &NJATA32_REGH(sc))
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!= 0) {
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/* failed -- undo map and try I/O */
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Cardbus_mapreg_unmap(csc->sc_ct,
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NJATA32_CARDBUS_BASEADDR_MEM, NJATA32_REGT(sc),
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csc->sc_regmaph, csc->sc_regmap_size);
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goto try_io;
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}
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#ifdef NJATA32_DEBUG
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aprint_normal("%s: memory space mapped, size %u\n",
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NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
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#endif
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csr |= PCI_COMMAND_MEM_ENABLE;
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sc->sc_flags = NJATA32_MEM_MAPPED;
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} else {
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try_io:
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if (Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
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PCI_MAPREG_TYPE_IO, 0, &NJATA32_REGT(sc),
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&NJATA32_REGH(sc), NULL, &csc->sc_regmap_size) == 0) {
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#ifdef NJATA32_DEBUG
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aprint_normal("%s: io space mapped, size %u\n",
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NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
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#endif
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csr |= PCI_COMMAND_IO_ENABLE;
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sc->sc_flags = NJATA32_IO_MAPPED;
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} else {
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aprint_error("%s: unable to map device registers\n",
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NJATA32NAME(sc));
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return;
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}
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}
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/* Enable the appropriate bits in the PCI CSR. */
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reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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reg |= csr;
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Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
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if (PCI_LATTIMER(reg) < latency) {
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reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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reg |= (latency << PCI_LATTIMER_SHIFT);
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Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
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}
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sc->sc_dmat = ca->ca_dmat;
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/*
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* Establish the interrupt.
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*/
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sc->sc_ih = Cardbus_intr_establish(ct, ca->ca_intrline, IPL_BIO,
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njata32_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error("%s: unable to establish interrupt\n",
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NJATA32NAME(sc));
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return;
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}
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/* attach */
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njata32_attach(sc);
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}
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static int
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njata_cardbus_detach(device_t self, int flags)
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{
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struct njata32_cardbus_softc *csc = device_private(self);
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struct njata32_softc *sc = &csc->sc_njata32;
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int rv;
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rv = njata32_detach(sc, flags);
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if (rv)
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return rv;
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if (sc->sc_ih)
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Cardbus_intr_disestablish(csc->sc_ct, sc->sc_ih);
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if (sc->sc_flags & NJATA32_IO_MAPPED)
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Cardbus_mapreg_unmap(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
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NJATA32_REGT(sc), NJATA32_REGH(sc), csc->sc_regmap_size);
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if (sc->sc_flags & NJATA32_MEM_MAPPED)
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Cardbus_mapreg_unmap(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
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NJATA32_REGT(sc), csc->sc_regmaph, csc->sc_regmap_size);
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return 0;
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}
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