308 lines
8.3 KiB
C
308 lines
8.3 KiB
C
/* $NetBSD: ahc_cardbus.c,v 1.9 2002/10/02 16:33:40 thorpej Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* CardBus front-end for the Adaptec AIC-7xxx family of SCSI controllers.
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*
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* TODO:
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* - power management
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ahc_cardbus.c,v 1.9 2002/10/02 16:33:40 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/queue.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/pci/pcireg.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/cardbus/cardbusdevs.h>
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#include <dev/ic/aic7xxxvar.h>
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#include <dev/microcode/aic7xxx/aic7xxx_reg.h>
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#define AHC_CARDBUS_IOBA 0x10
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#define AHC_CARDBUS_MMBA 0x14
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struct ahc_cardbus_softc {
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struct ahc_softc sc_ahc; /* real AHC */
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/* CardBus-specific goo. */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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int sc_intrline; /* our interrupt line */
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cardbustag_t sc_tag;
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int sc_cbenable; /* what CardBus access type to enable */
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int sc_csr; /* CSR bits */
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bus_size_t sc_size;
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};
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int ahc_cardbus_match __P((struct device *, struct cfdata *, void *));
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void ahc_cardbus_attach __P((struct device *, struct device *, void *));
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int ahc_cardbus_detach __P((struct device *, int));
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CFATTACH_DECL(ahc_cardbus, sizeof(struct ahc_cardbus_softc),
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ahc_cardbus_match, ahc_cardbus_attach, ahc_cardbus_detach, ahc_activate);
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int
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ahc_cardbus_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct cardbus_attach_args *ca = aux;
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if (CARDBUS_VENDOR(ca->ca_id) == CARDBUS_VENDOR_ADP &&
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CARDBUS_PRODUCT(ca->ca_id) == CARDBUS_PRODUCT_ADP_1480)
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return (1);
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return (0);
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}
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void
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ahc_cardbus_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct cardbus_attach_args *ca = aux;
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struct ahc_cardbus_softc *csc = (void *) self;
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struct ahc_softc *ahc = &csc->sc_ahc;
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cardbus_devfunc_t ct = ca->ca_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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pcireg_t reg;
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u_int sxfrctl1 = 0;
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ahc_chip ahc_t = AHC_NONE;
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ahc_feature ahc_fe = AHC_FENONE;
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ahc_flag ahc_f = AHC_FNONE;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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csc->sc_intrline = ca->ca_intrline;
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printf(": Adaptec ADP-1480 SCSI\n");
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/*
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* Map the device.
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*/
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csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
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if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_MMBA,
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PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&bst, &bsh, NULL, &csc->sc_size) == 0) {
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csc->sc_cbenable = CARDBUS_MEM_ENABLE;
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csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
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} else if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_IOBA,
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PCI_MAPREG_TYPE_IO, 0, &bst, &bsh, NULL, &csc->sc_size) == 0) {
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csc->sc_cbenable = CARDBUS_IO_ENABLE;
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csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
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} else {
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printf("%s: unable to map device registers\n",
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ahc_name(ahc));
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return;
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}
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/* Make sure the right access type is on the CardBus bridge. */
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(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable);
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(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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reg |= csc->sc_csr;
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cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG);
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if (PCI_LATTIMER(reg) < 0x20) {
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reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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reg |= (0x20 << PCI_LATTIMER_SHIFT);
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cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg);
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}
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ahc->tag = bst;
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ahc->bsh = bsh;
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/*
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* ADP-1480 is always an AIC-7860.
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*/
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ahc_t = AHC_AIC7860;
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ahc_fe = AHC_AIC7860_FE;
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/*
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* On all CardBus adapters, we allow SCB paging.
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*/
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ahc_f = AHC_PAGESCBS;
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if (ahc_alloc(ahc, bsh, bst, ca->ca_dmat, ahc_t | AHC_PCI /* XXX */,
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ahc_fe, ahc_f) < 0) {
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printf("%s: unable to initialize softc\n", ahc_name(ahc));
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return;
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}
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ahc->channel = 'A';
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ahc_reset(ahc);
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/*
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* Establish the interrupt.
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*/
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ahc->ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
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ahc_intr, ahc);
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if (ahc->ih == NULL) {
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printf("%s: unable to establish interrupt at %d\n",
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ahc_name(ahc), ca->ca_intrline);
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return;
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}
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printf("%s: interrupting at %d\n", ahc_name(ahc), ca->ca_intrline);
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/*
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* Do chip-specific initialization.
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*/
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{
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u_char sblkctl;
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const char *id_string;
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switch (ahc->chip & AHC_CHIPID_MASK) {
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case AHC_AIC7860:
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id_string = "aic7860 ";
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check_extport(ahc, &sxfrctl1);
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break;
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default:
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printf("%s: unknown controller type\n", ahc_name(ahc));
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ahc_free(ahc);
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return;
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}
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/*
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* Take the LED out of diagnostic mode.
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*/
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sblkctl = ahc_inb(ahc, SBLKCTL);
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ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
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/*
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* I don't know where this is set in the SEEPROM or by the
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* BIOS, so we default to 100%.
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*/
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ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
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if (ahc->flags & AHC_USEDEFAULTS) {
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/*
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* We can't "use defaults", as we have no way
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* of knowing what default settings hould be.
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*/
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printf("%s: CardBus device requires an SEEPROM\n",
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ahc_name(ahc));
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return;
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}
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printf("%s: %s", ahc_name(ahc), id_string);
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}
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/*
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* XXX does this card have external SRAM? - fvdl
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*/
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/*
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* Record our termination setting for the
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* generic initialization routine.
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*/
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if ((sxfrctl1 & STPWEN) != 0)
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ahc->flags |= AHC_TERM_ENB_A;
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if (ahc_init(ahc)) {
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ahc_free(ahc);
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return;
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}
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ahc_attach(ahc);
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}
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int
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ahc_cardbus_detach(self, flags)
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struct device *self;
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int flags;
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{
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struct ahc_cardbus_softc *csc = (void*)self;
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struct ahc_softc *ahc = &csc->sc_ahc;
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int rv;
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rv = ahc_detach(ahc, flags);
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if (rv)
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return rv;
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if (ahc->ih) {
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cardbus_intr_disestablish(csc->sc_ct->ct_cc,
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csc->sc_ct->ct_cf, ahc->ih);
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ahc->ih = 0;
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}
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if (csc->sc_cbenable) {
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if (csc->sc_cbenable == CARDBUS_MEM_ENABLE)
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Cardbus_mapreg_unmap(csc->sc_ct, AHC_CARDBUS_MMBA,
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ahc->tag, ahc->bsh, csc->sc_size);
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else if (csc->sc_cbenable == CARDBUS_IO_ENABLE)
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Cardbus_mapreg_unmap(csc->sc_ct, AHC_CARDBUS_IOBA,
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ahc->tag, ahc->bsh, csc->sc_size);
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csc->sc_cbenable = 0;
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}
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return (0);
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}
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