249 lines
8.8 KiB
C
249 lines
8.8 KiB
C
/* $NetBSD: s3c24x0reg.h,v 1.5 2003/09/03 03:12:28 mycroft Exp $ */
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/*
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* Copyright (c) 2003 Genetec corporation All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Samsung S3C2410X/2400 processor is ARM920T based integrated CPU
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*
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* Reference:
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* S3C2410X User's Manual
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* S3C2400 User's Manual
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*/
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#ifndef _ARM_S3C2XX0_S3C24X0REG_H_
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#define _ARM_S3C2XX0_S3C24X0REG_H_
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/* Memory controller */
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#define MEMCTL_BWSCON 0x00 /* Bus width and wait status */
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#define BWSCON_DW0_SHIFT 1 /* bank0 is odd */
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#define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */
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#define BWSCON_DW_MASK 0x03
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#define BWSCON_DW_8 0
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#define BWSCON_DW_16 1
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#define BWSCON_DW_32 2
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#define BWSCON_WS 0x04 /* WAIT enable for the bank */
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#define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */
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#define MEMCTL_BANKCON0 0x04 /* Boot ROM control */
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#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */
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#define BANKCON_MT_SHIFT 15
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#define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT)
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#define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT)
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#define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */
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#define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */
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#define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */
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#define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */
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#define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */
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#define BANKCON_TACP_SHIFT 2 /* page mode access cycle */
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#define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT)
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#define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT)
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#define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT)
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#define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT)
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#define BANKCON_PMC_4 (1<<0)
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#define BANKCON_PMC_8 (2<<0)
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#define BANKCON_PMC_16 (3<<0)
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#define BANKCON_TRCD_SHIFT 2 /* RAS to CAS delay */
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#define BANKCON_TRCD_2 (0<<2)
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#define BANKCON_TRCD_3 (1<<2)
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#define BANKCON_TRCD_4 (2<<2)
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#define BANKCON_SCAN_8 (0<<0) /* Column address number */
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#define BANKCON_SCAN_9 (1<<0)
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#define BANKCON_SCAN_10 (2<<0)
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#define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */
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#define REFRESH_REFEN (1<<23)
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#define REFRESH_TREFMD (1<<22) /* 1=self refresh */
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#define REFRESH_TRP_2 (0<<20)
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#define REFRESH_TRP_3 (1<<20)
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#define REFRESH_TRP_4 (2<<20)
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#define REFRESH_TRC_4 (0<<18)
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#define REFRESH_TRC_5 (1<<18)
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#define REFRESH_TRC_6 (2<<18)
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#define REFRESH_TRC_7 (3<<18)
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#define REFRESH_COUNTER_MASK 0x3ff
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#define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */
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#define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */
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#define MEMCTL_MRSRB7 0x30
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#define MRSR_CL_SHIFT 4 /* CAS Latency */
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#define S3C24X0_MEMCTL_SIZE 0x34
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/* USB Host controller */
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#define S3C24X0_USBHC_SIZE 0x5c
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/* Interrupt controller */
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#define INTCTL_PRIORITY 0x0c /* IRQ Priority control */
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#define INTCTL_INTPND 0x10 /* Interrupt request status */
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#define INTCTL_INTOFFSET 0x14 /* Interrupt request source */
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/* Interrupt source */
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#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410 */
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#define S3C24X0_INT_RTC 30 /* RTC alarm */
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#define S3C2400_INT_UTXD1 29 /* UART1 Tx INT (2400 only) */
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#define S3C2410_INT_SPI1 29 /* SPI 1 (2410 only) */
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#define S3C2400_INT_UTXD0 28 /* UART0 Tx INT (2400 only) */
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#define S3C2410_INT_UART0 28 /* UART0 (2410 only) */
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#define S3C24X0_INT_IIC 27
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#define S3C24X0_INT_USBH 26 /* USB Host */
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#define S3C24X0_INT_USBD 25 /* USB Device */
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#define S3C2400_INT_URXD1 24 /* UART1 Rx INT (2400 only) */
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#define S3C2400_INT_URXD0 23 /* UART0 Rx INT (2400 only) */
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#define S3C2410_INT_UART1 23 /* UART0 (2410 only) */
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#define S3C24X0_INT_SPI0 22 /* SPI 0 */
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#define S3C2400_INT_MMC 21
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#define S3C2410_INT_SDI 21
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#define S3C24X0_INT_DMA3 20
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#define S3C24X0_INT_DMA2 19
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#define S3C24X0_INT_DMA1 18
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#define S3C24X0_INT_DMA0 17
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#define S3C2410_INT_LCD 16
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#define S3C2400_INT_UERR 15 /* UART 0/1 Error int (2400) */
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#define S3C2410_INT_UART2 15 /* UART2 int (2410) */
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#define S3C24X0_INT_TIMER4 14
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#define S3C24X0_INT_TIMER3 13
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#define S3C24X0_INT_TIMER2 12
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#define S3C24X0_INT_TIMER1 11
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#define S3C24X0_INT_TIMER0 10
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#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */
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#define S3C24X0_INT_WDT 9 /* Watch dog timer */
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#define S3C24X0_INT_TICK 8
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#define S3C2410_INT_BFLT 7 /* Battery fault */
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#define S3C2410_INT_8_23 5 /* Ext int 8..23 */
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#define S3C2410_INT_4_7 4 /* Ext int 4..7 */
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#define S3C24X0_INT_EXT(n) (n) /* External interrupt [7:0] for 2400,
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* [3:0] for 2410 */
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/* DMA controller */
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/* XXX */
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/* Clock & power manager */
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#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */
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#define CLKMAN_MPLLCON 0x04 /* MPLL control */
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#define CLKMAN_UPLLCON 0x08 /* UPLL control */
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#define PLLCON_MDIV_SHIFT 12
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#define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT)
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#define PLLCON_PDIV_SHIFT 4
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#define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT)
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#define PLLCON_SDIV_SHIFT 0
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#define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT)
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#define CLKMAN_CLKCON 0x0c
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#define CLKMAN_CLKSLOW 0x10 /* slow clock controll */
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#define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */
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#define CLKSLOW_MPLL (1<<5) /* 1=PLL off */
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#define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */
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#define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */
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#define CLKMAN_CLKDIVN 0x14 /* Software reset control */
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#define CLKDIVN_HDIVN (1<<1)
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#define CLKDIVN_PDIVN (1<<0)
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#define S3C24X0_CLKMAN_SIZE 0x18
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/* LCD controller */
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/* XXX */
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#define S3C24X0_LCDC_SIZE 0x64
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/* Timer */
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#define TIMER_TCFG0 0x00 /* Timer configuration */
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#define TIMER_TCFG1 0x04
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#define TCFG1_MUX_SHIFT(n) (4*(n))
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#define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n))
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#define TCFG1_MUX_DIV2 0
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#define TCFG1_MUX_DIV4 1
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#define TCFG1_MUX_DIV8 2
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#define TCFG1_MUX_DIV16 3
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#define TCFG1_MUX_EXT 4
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#define TIMER_TCON 0x08 /* control */
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#define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1))
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#define TCON_START(n) (1 << TCON_SHIFT(n))
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#define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1))
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#define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2))
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#define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */
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#define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */
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#define TCON_AUTORELOAD(n) ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n))
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#define TCON_MASK(n) (0x0f << TCON_SHIFT(n))
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#define TIMER_TCNTB(n) (0x0c+0x0c*(n)) /* count buffer */
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#define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer */
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#define __TIMER_TCNTO(n) (0x14+0x0c*(n)) /* count observation */
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#define TIMER_TCNTO4 0x40
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#define TIMER_TCNTO(n) ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n))
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#define S3C24X0_TIMER_SIZE 0x44
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/* UART */
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/* diffs to s3c2800 */
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#define UMCON_AFC (1<<4) /* auto flow control */
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#define UMSTAT_DCTS (1<<2) /* CTS change */
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#define ULCON_IR (1<<6)
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#define ULCON_PARITY_SHIFT 3
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#define S3C24X0_UART_SIZE 0x2c
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/* USB device */
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/* XXX */
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/* Watch dog timer */
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#define WDT_WTCON 0x00 /* WDT mode */
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#define WTCON_PRESCALE_SHIFT 8
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#define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT)
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#define WTCON_ENABLE (1<<5)
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#define WTCON_CLKSEL (3<<3)
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#define WTCON_CLKSEL_16 (0<<3)
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#define WTCON_CLKSEL_32 (1<<3)
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#define WTCON_CLKSEL_64 (2<<3)
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#define WTCON_CLKSEL_128 (3<<3)
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#define WTCON_ENINT (1<<2)
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#define WTCON_ENRST (1<<0)
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#define WTCON_WDTSTOP 0
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#define WDT_WTDAT 0x04 /* timer data */
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#define WDT_WTCNT 0x08 /* timer count */
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#define S3C24X0_WDT_SIZE 0x0c
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/* IIC */ /* XXX */
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#define S3C24X0_IIC_SIZE 0x0c
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/* IIS */ /* XXX */
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#define S3C24X0_IIS_SIZE 0x14
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/* RTC */ /* XXX */
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/* ADC */ /* XXX */
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/* SPI */ /* XXX */
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#define S3C24X0_SPI_SIZE 0x18
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#endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */
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