6d6c652f18
utilizing David Jones' new MI NCR 5380 code. Ported from the sun3 ncr_si.c and "sw" DMA code written by me. This driver contains user-configurable "options", which can be set via the "flags" directive in the kernel configuration file. By default, only DMA is enabled. DMA completion interrupts and reselection may be enabled by setting the appropriate bits with "flags". See si.c for details. Note that DMA completion interrupts and reselection don't yet work on the 4/100 controller. I don't know why, and it's unlikely that I'll have the opportunity to find out any time soon. DMA does work, and results in a considerable performance increase. DMA, DMA completion interrupts, and reslection all work on my 4/260 (VME) system with modern SCSI-II disks.
128 lines
4.2 KiB
C
128 lines
4.2 KiB
C
/* $NetBSD: sireg.h,v 1.3 1996/01/01 22:40:58 thorpej Exp $ */
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/*
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* Register map for the Sun3 SCSI Interface (si)
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* The first part of this register map is an NCR5380
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* SCSI Bus Interface Controller (SBIC). The rest is a
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* DMA controller and custom logic in one of two flavors,
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* one for the OBIO interface (3/50,3/60) and one for the
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* VME interface (3/160,3/260,etc.), where some registers
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* are implemented only on one or the other, some on both.
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*
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* Modified for Sun 4 systems by Jason R. Thorpe <thorpej@NetBSD.ORG>.
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*/
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/*
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* Note that the obio version on the 4/1xx (the so-called "SCSI Weird", or
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* "sw" controller) is laid out a bit differently, and hence the evilness
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* with unions. Also, the "sw" doesn't appear to have a FIFO.
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*/
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/*
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* Am5380 Register map (no padding)
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*/
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struct ncr5380regs {
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volatile u_char sci_r0;
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volatile u_char sci_r1;
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volatile u_char sci_r2;
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volatile u_char sci_r3;
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volatile u_char sci_r4;
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volatile u_char sci_r5;
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volatile u_char sci_r6;
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volatile u_char sci_r7;
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};
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struct si_regs {
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struct ncr5380regs sci;
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/* DMA controller registers */
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union {
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struct {
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u_short _Dma_addrh; /* dma address (VME only) */
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u_short _Dma_addrl; /* (high word, low word) */
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} _si_u1_s;
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u_int _Dma_addr; /* dma address (OBIO) */
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} _si_u1;
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#define dma_addrh _si_u1._si_u1_s._Dma_addrh
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#define dma_addrl _si_u1._si_u1_s._Dma_addrl
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#define dma_addr _si_u1._Dma_addr
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union {
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struct {
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u_short _Dma_counth; /* dma count (VME only) */
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u_short _Dma_countl; /* (high word, low word) */
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} _si_u2_s;
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u_int _Dma_count; /* dma count (OBIO) */
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} _si_u2;
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#define dma_counth _si_u2._si_u2_s._Dma_counth
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#define dma_countl _si_u2._si_u2_s._Dma_countl
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#define dma_count _si_u2._Dma_count
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u_int si_pad0; /* no-existent register */
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union {
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struct {
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u_short _Fifo_data; /* fifo data register */
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u_short _Fifo_count; /* fifo count register */
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} _si_u4_s;
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u_int _Sw_csr; /* sw control/status */
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} _si_u4;
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#define fifo_data _si_u4._si_u4_s._Fifo_data
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#define fifo_count _si_u4._si_u4_s._Fifo_count
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#define sw_csr _si_u4._Sw_csr
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union {
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struct {
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u_short _Si_csr; /* si control/status */
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u_short _Bprh; /* VME byte pack high */
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} _si_u5_s;
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u_int _Bpr; /* sw byte pack */
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} _si_u5;
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#define si_csr _si_u5._si_u5_s._Si_csr
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#define si_bprh _si_u5._si_u5_s._Bprh
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#define sw_bpr _si_u5._Bpr
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/* The rest of these are on the VME interface only: */
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u_short si_bprl; /* VME byte pack low */
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u_short si_iv_am; /* bits 0-7: intr vector */
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/* bits 8-13: addr modifier (VME only) */
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/* bits 14-15: unused */
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u_short fifo_cnt_hi; /* high part of fifo_count (VME only) */
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/* Whole thing repeats after 32 bytes. */
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u_short _space[3];
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};
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/* possible values for the address modifier, vme version only */
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#define VME_SUPV_DATA_24 0x3d00
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/*
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* Status Register.
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* Note:
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* (r) indicates bit is read only.
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* (rw) indicates bit is read or write.
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* (v) vme host adaptor interface only.
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* (o) sun3/50 onboard host adaptor interface only.
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* (b) both vme and sun3/50 host adaptor interfaces.
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*/
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#define SI_CSR_DMA_ACTIVE 0x8000 /* (r,o) dma transfer active */
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#define SI_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while dmaing */
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#define SI_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during dma */
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#define SI_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */
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/* 0 if SCSI-3 unmodified */
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#define SI_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */
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#define SI_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */
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#define SI_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */
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#define SI_CSR_DMA_IP 0x0100 /* (r,b) dma interrupt pending */
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#define SI_CSR_LOB 0x00c0 /* (r,v) number of leftover bytes */
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#define SI_CSR_LOB_THREE 0x00c0 /* (r,v) three leftover bytes */
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#define SI_CSR_LOB_TWO 0x0080 /* (r,v) two leftover bytes */
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#define SI_CSR_LOB_ONE 0x0040 /* (r,v) one leftover byte */
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#define SI_CSR_BPCON 0x0020 /* (rw,v) byte packing control */
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/* dma is in 0=longwords, 1=words */
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#define SI_CSR_DMA_EN 0x0010 /* (rw,v) dma/interrupt enable */
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#define SI_CSR_SEND 0x0008 /* (rw,b) dma dir, 1=to device */
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#define SI_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */
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#define SI_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */
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#define SI_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */
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