157 lines
6.0 KiB
C
157 lines
6.0 KiB
C
/* $NetBSD: vrpiureg.h,v 1.1 1999/12/28 03:15:18 takemura Exp $ */
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/*
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* Copyright (c) 1999 Shin Takemura All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* PIU (Touch panel interface unit) register definitions
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*/
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#define PIUCNT_REG_W 0x002 /* PIU Control register */
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#define PIUCNT_PENSTC (1<<13)
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#define PIUCNT_PADSTATE_MASK (0x7<<10)
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#define PIUCNT_PADSTATE_SHIFT 10
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#define PIUCNT_PADSTATE_CmdScan (0x7<<10)
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#define PIUCNT_PADSTATE_IntervalNextScan (0x6<<10)
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#define PIUCNT_PADSTATE_PenDataScan (0x5<<10)
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#define PIUCNT_PADSTATE_WaitPenTouch (0x4<<10)
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#define PIUCNT_PADSTATE_RFU (0x3<<10)
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#define PIUCNT_PADSTATE_ADPortScan (0x2<<10)
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#define PIUCNT_PADSTATE_Standby (0x1<<10)
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#define PIUCNT_PADSTATE_Disable (0x0<<10)
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#define PIUCNT_PADATSTOP (1<<9)
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#define PIUCNT_PADATSTART (1<<8)
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#define PIUCNT_PADSCANSTOP (1<<7)
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#define PIUCNT_PADSCANSTART (1<<6)
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#define PIUCNT_PADSCANTYPE (1<<5)
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#define PIUCNT_PIUMODE_MASK (0x3<<3)
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#define PIUCNT_PIUMODE_ADCONVERTER (0x1<<3)
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#define PIUCNT_PIUMODE_COORDINATE (0x0<<3)
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#define PIUCNT_PIUSEQEN (1<<2)
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#define PIUCNT_PIUPWR (1<<1)
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#define PIUCNT_PADRST (1<<0)
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#define PIUINT_REG_W 0x004 /* PIU Interruptcause register */
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#define PIUINT_OVP (1<<15)
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#define PIUINT_PADCMDINTR (1<<6)
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#define PIUINT_PADADPINTR (1<<5)
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#define PIUINT_PADPAGE1INTR (1<<4)
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#define PIUINT_PADPAGE0INTR (1<<3)
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#define PIUINT_PADDLOSTINTR (1<<2)
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#define PIUINT_PENCHGINTR (1<<0)
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#define PIUINT_ALLINTR (PIUINT_PADCMDINTR | \
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PIUINT_PADADPINTR | \
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PIUINT_PADPAGE1INTR | \
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PIUINT_PADPAGE0INTR | \
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PIUINT_PADDLOSTINTR | \
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PIUINT_PENCHGINTR)
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#define PIUSIVL_REG_W 0x006 /* PIU Data sampling interval register */
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#define PIUSIVL_SCANINTVAL_MASK 0x7FF
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#define PIUSIVL_SCANINTVAL_UNIT 30 /* 30 us */
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#define PIUSTBL_REG_W 0x008 /* PIU A/D converter start delay register*/
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#define PIUSTBL_STABLE_MASK 0x1F
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#define PIUSTBL_STABLE_UNIT 30 /* 30 us */
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#define PIUCMD_REG_W 0x00A /* PIU A/D command register */
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#define PIUCMD_STABLEON (1<<12)
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#define PIUCMD_TPYEN_MASK (3<<10)
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#define PIUCMD_TPY1_INPUT (0<<11)
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#define PIUCMD_TPY1_OUTPUT (1<<11)
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#define PIUCMD_TPY0_INPUT (0<<10)
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#define PIUCMD_TPY0_OUTPUT (1<<10)
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#define PIUCMD_TPXEN_MASK (3<<8)
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#define PIUCMD_TPX1_INPUT (0<<9)
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#define PIUCMD_TPX1_OUTPUT (1<<9)
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#define PIUCMD_TPX0_INPUT (0<<8)
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#define PIUCMD_TPX0_OUTPUT (1<<8)
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#define PIUCMD_TPYD_MASK (3<<6)
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#define PIUCMD_TPY1_LOW (0<<7)
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#define PIUCMD_TPY1_HIGH (1<<7)
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#define PIUCMD_TPY0_LOW (0<<6)
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#define PIUCMD_TPY0_HIGH (1<<6)
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#define PIUCMD_TPXD_MASK (3<<4)
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#define PIUCMD_TPX1_LOW (0<<5)
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#define PIUCMD_TPX1_HIGH (1<<5)
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#define PIUCMD_TPX0_LOW (0<<4)
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#define PIUCMD_TPX0_HIGH (1<<4)
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#define PIUCMD_ADCMD_MASK 0xF
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#define PIUCMD_STANBYREQ 0xF
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#define PIUCMD_AUDIOIN 0x7
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#define PIUCMD_ADIN2 0x6
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#define PIUCMD_ADIN1 0x5
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#define PIUCMD_ADIN0 0x4
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#define PIUCMD_TPY1 0x3
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#define PIUCMD_TPY0 0x2
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#define PIUCMD_TPX1 0x1
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#define PIUCMD_TPX0 0x0
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#define PIUASCN_REG_W 0x010 /* PIU A/D port scan register */
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#define PIUACN_TPPSCAN (1<<1)
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#define PIUACN_ADPSSTART (1<<0)
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#define PIUAMSK_REG_W 0x012 /* PIU A/D scan mask register */
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#define PIUAMSK_ADINM3 (1<<7)
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#define PIUAMSK_AUDIOM PIUAMSK_ADINM3
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#define PIUAMSK_ADINM2 (1<<6)
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#define PIUAMSK_ADINM1 (1<<5)
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#define PIUAMSK_ADINM0 (1<<4)
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#define PIUAMSK_ADINMALL 0x70
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#define PIUAMSK_TPYM1 (1<<3)
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#define PIUAMSK_TPYM0 (1<<2)
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#define PIUAMSK_TPXM1 (1<<1)
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#define PIUAMSK_TPXM0 (1<<0)
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#define PIUAMSK_TPMALL 0xF0
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#define PIUCIVL_REG_W 0x01E /* PIU Check interval register */
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#define PIUCIVL_CHKINTVAL_MASK 0x7FF
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#define PIUPB00_REG_W 0x180 /* PIU Page 0 Buffer 0 register */
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#define PIUPB01_REG_W 0x182 /* PIU Page 0 Buffer 1 register */
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#define PIUPB02_REG_W 0x184 /* PIU Page 0 Buffer 2 register */
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#define PIUPB03_REG_W 0x186 /* PIU Page 0 Buffer 3 register */
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#define PIUPB04_REG_W 0x19C /* PIU Page 0 Buffer 4 register */
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#define PIUPB10_REG_W 0x188 /* PIU Page 1 Buffer 0 register */
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#define PIUPB11_REG_W 0x18A /* PIU Page 1 Buffer 1 register */
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#define PIUPB12_REG_W 0x18C /* PIU Page 1 Buffer 2 register */
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#define PIUPB13_REG_W 0x18E /* PIU Page 1 Buffer 3 register */
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#define PIUPB14_REG_W 0x19E /* PIU Page 1 Buffer 4 register */
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#define PIUPB(page, n) (((n)<4) ? \
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(0x180 + (page) * 8 + (n) * 2) : \
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(0x19C + (page) * 2))
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#define PIUPB_VALID (1<<15)
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#define PIUPB_PADDATA_MASK 0x3FF
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#define PIUPB_PADDATA_MAX 0x3FF
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#define PIUAB0_REG_W 0x190 /* PIU A/D scan Buffer 0 register */
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#define PIUAB1_REG_W 0x192 /* PIU A/D scan Buffer 1 register */
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#define PIUAB2_REG_W 0x194 /* PIU A/D scan Buffer 2 register */
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#define PIUAB3_REG_W 0x196 /* PIU A/D scan Buffer 3 register */
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#define PIUAB_VALID (1<<15)
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#define PIUAB_PADDATA_MASK 0x3FF
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