430 lines
10 KiB
C
430 lines
10 KiB
C
/* $NetBSD: piixpcib.c,v 1.21 2011/07/01 17:37:27 dyoung Exp $ */
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/*-
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* Copyright (c) 2004, 2006 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Minoura Makoto, Matthew R. Green, and Jared D. McNeill.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support
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*
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* Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.21 2011/07/01 17:37:27 dyoung Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/sysctl.h>
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#include <sys/bus.h>
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#include <machine/frame.h>
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#include <machine/bioscall.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/piixreg.h>
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#include <x86/pci/pcibvar.h>
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#define PIIX4_PIRQRC 0x60
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struct piixpcib_softc {
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/* we call pcibattach() which assumes our softc starts like this: */
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struct pcib_softc sc_pcib;
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device_t sc_dev;
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int sc_smi_cmd;
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int sc_smi_data;
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int sc_command;
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int sc_flags;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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pcireg_t sc_pirqrc;
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uint8_t sc_elcr[2];
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};
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static int piixpcibmatch(device_t, cfdata_t, void *);
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static void piixpcibattach(device_t, device_t, void *);
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static bool piixpcib_suspend(device_t, const pmf_qual_t *);
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static bool piixpcib_resume(device_t, const pmf_qual_t *);
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static void speedstep_configure(struct piixpcib_softc *,
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const struct pci_attach_args *);
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static int speedstep_sysctl_helper(SYSCTLFN_ARGS);
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static struct piixpcib_softc *speedstep_cookie; /* XXX */
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CFATTACH_DECL_NEW(piixpcib, sizeof(struct piixpcib_softc),
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piixpcibmatch, piixpcibattach, NULL, NULL);
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/*
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* Autoconf callbacks.
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*/
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static int
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piixpcibmatch(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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/* We are ISA bridge, of course */
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if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
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(PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA &&
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PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) {
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return 0;
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}
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/* Matches only Intel PIIX4 */
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */
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case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */
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return 10;
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}
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}
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return 0;
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}
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static void
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piixpcibattach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct piixpcib_softc *sc = device_private(self);
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sc->sc_dev = self;
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sc->sc_iot = pa->pa_iot;
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pcibattach(parent, self, aux);
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/* Set up SpeedStep. */
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speedstep_configure(sc, pa);
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/* Map edge/level control registers */
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if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0,
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&sc->sc_ioh)) {
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aprint_error_dev(self, "can't map edge/level control registers\n");
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return;
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}
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if (!pmf_device_register(self, piixpcib_suspend, piixpcib_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static bool
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piixpcib_suspend(device_t dv, const pmf_qual_t *qual)
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{
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struct piixpcib_softc *sc = device_private(dv);
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/* capture PIRQX route control registers */
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sc->sc_pirqrc = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
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PIIX4_PIRQRC);
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/* capture edge/level control registers */
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sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0);
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sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1);
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return true;
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}
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static bool
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piixpcib_resume(device_t dv, const pmf_qual_t *qual)
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{
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struct piixpcib_softc *sc = device_private(dv);
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/* restore PIRQX route control registers */
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pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, PIIX4_PIRQRC,
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sc->sc_pirqrc);
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/* restore edge/level control registers */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]);
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return true;
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}
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/*
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* Intel PIIX4 (SMI) SpeedStep support.
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*/
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#define PIIXPCIB_GSIC 0x47534943
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#define PIIXPCIB_GETOWNER 0
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#define PIIXPCIB_GETSTATE 1
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#define PIIXPCIB_SETSTATE 2
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#define PIIXPCIB_GETFREQS 4
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#define PIIXPCIB_SPEEDSTEP_HIGH 0
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#define PIIXPCIB_SPEEDSTEP_LOW 1
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static void
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piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, int *flags)
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{
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struct bioscallregs regs;
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memset(®s, 0, sizeof(struct bioscallregs));
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regs.EAX = 0x0000e980; /* IST support */
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regs.EDX = PIIXPCIB_GSIC;
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bioscall(0x15, ®s);
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if (regs.EAX == PIIXPCIB_GSIC) {
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*sig = regs.EAX;
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*smicmd = regs.EBX & 0xff;
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*cmd = (regs.EBX >> 16) & 0xff;
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*smidata = regs.ECX;
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*flags = regs.EDX;
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} else
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*sig = *smicmd = *cmd = *smidata = *flags = -1;
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return;
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}
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static int
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piixpcib_set_ownership(struct piixpcib_softc *sc)
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{
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int rv;
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u_long pmagic;
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static char magic[] = "Copyright (c) 1999 Intel Corporation";
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pmagic = vtophys((vaddr_t)magic);
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__asm__ __volatile__(
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"movl $0, %%edi\n\t"
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"out %%al, (%%dx)\n"
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: "=D" (rv)
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: "a" (sc->sc_command),
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"b" (0),
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"c" (0),
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"d" (sc->sc_smi_cmd),
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"S" (pmagic)
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);
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return (rv ? ENXIO : 0);
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}
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static int
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piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function)
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{
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int new;
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int rv;
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int eax;
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#ifdef DIAGNOSTIC
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if (function != PIIXPCIB_GETSTATE &&
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function != PIIXPCIB_SETSTATE) {
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aprint_error_dev(sc->sc_dev, "GSI called with invalid function %d\n",
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function);
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return EINVAL;
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}
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#endif
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__asm__ __volatile__(
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"movl $0, %%edi\n\t"
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"out %%al, (%%dx)\n"
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: "=a" (eax),
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"=b" (new),
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"=D" (rv)
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: "a" (sc->sc_command),
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"b" (function),
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"c" (*state),
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"d" (sc->sc_smi_cmd),
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"S" (0)
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);
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*state = new & 1;
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switch (function) {
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case PIIXPCIB_GETSTATE:
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if (eax)
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return ENXIO;
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break;
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case PIIXPCIB_SETSTATE:
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if (rv)
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return ENXIO;
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break;
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}
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return 0;
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}
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static int
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piixpcib_get(struct piixpcib_softc *sc)
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{
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int rv;
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int state;
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state = 0; /* XXX gcc */
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rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE);
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if (rv)
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return rv;
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return state & 1;
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}
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static int
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piixpcib_set(struct piixpcib_softc *sc, int state)
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{
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int rv, s;
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int try;
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if (state != PIIXPCIB_SPEEDSTEP_HIGH &&
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state != PIIXPCIB_SPEEDSTEP_LOW)
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return ENXIO;
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if (piixpcib_get(sc) == state)
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return 0;
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try = 5;
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s = splhigh();
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do {
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rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE);
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if (rv)
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delay(200);
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} while (rv && --try);
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splx(s);
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return rv;
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}
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static void
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speedstep_configure(struct piixpcib_softc *sc,
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const struct pci_attach_args *pa)
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{
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const struct sysctlnode *node, *ssnode;
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int sig, smicmd, cmd, smidata, flags;
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int rv;
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piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags);
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if (sig != -1) {
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sc->sc_smi_cmd = smicmd;
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sc->sc_smi_data = smidata;
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if (cmd == 0x80) {
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aprint_debug_dev(sc->sc_dev, "GSIC returned cmd 0x80, should be 0x82\n");
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cmd = 0x82;
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}
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sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff);
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sc->sc_flags = flags;
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} else {
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/* setup some defaults */
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sc->sc_smi_cmd = 0xb2;
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sc->sc_smi_data = 0xb3;
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sc->sc_command = 0x47534982;
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sc->sc_flags = 0;
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}
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if (piixpcib_set_ownership(sc) != 0) {
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aprint_error_dev(sc->sc_dev, "unable to claim ownership from the BIOS\n");
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return; /* If we can't claim ownership from the BIOS, bail */
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}
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/* Put in machdep.speedstep_state (0 for low, 1 for high). */
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if ((rv = sysctl_createv(NULL, 0, NULL, &node,
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CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
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NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0)
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goto err;
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/* CTLFLAG_ANYWRITE? kernel option like EST? */
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if ((rv = sysctl_createv(NULL, 0, &node, &ssnode,
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CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL,
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speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE,
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CTL_EOL)) != 0)
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goto err;
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/* XXX save the sc for IO tag/handle */
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speedstep_cookie = sc;
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aprint_verbose_dev(sc->sc_dev, "SpeedStep SMI enabled\n");
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return;
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err:
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aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv);
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}
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/*
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* get/set the SpeedStep state: 0 == low power, 1 == high power.
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*/
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static int
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speedstep_sysctl_helper(SYSCTLFN_ARGS)
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{
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struct sysctlnode node;
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struct piixpcib_softc *sc;
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uint8_t state, state2;
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int ostate, nstate, error;
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sc = speedstep_cookie;
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error = 0;
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state = piixpcib_get(sc);
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if (state == PIIXPCIB_SPEEDSTEP_HIGH)
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ostate = 1;
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else
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ostate = 0;
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nstate = ostate;
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node = *rnode;
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node.sysctl_data = &nstate;
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error = sysctl_lookup(SYSCTLFN_CALL(&node));
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if (error || newp == NULL)
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goto out;
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/* Only two states are available */
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if (nstate != 0 && nstate != 1) {
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error = EINVAL;
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goto out;
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}
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state2 = piixpcib_get(sc);
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if (state2 == PIIXPCIB_SPEEDSTEP_HIGH)
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ostate = 1;
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else
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ostate = 0;
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if (ostate != nstate)
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{
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if (nstate == 0)
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state2 = PIIXPCIB_SPEEDSTEP_LOW;
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else
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state2 = PIIXPCIB_SPEEDSTEP_HIGH;
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error = piixpcib_set(sc, state2);
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}
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out:
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return (error);
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}
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