212 lines
5.6 KiB
C
212 lines
5.6 KiB
C
/*
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* Copyright 1996 1995 by Open Software Foundation, Inc. 1997 1996 1995 1994 1993 1992 1991
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* All Rights Reserved
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies and
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* that both the copyright notice and this permission notice appear in
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* supporting documentation.
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*
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* OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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* NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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* WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef _POWERMAC_DBDMA_H_
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#define _POWERMAC_DBDMA_H_
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#define DBDMA_CMD_OUT_MORE 0
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#define DBDMA_CMD_OUT_LAST 1
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#define DBDMA_CMD_IN_MORE 2
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#define DBDMA_CMD_IN_LAST 3
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#define DBDMA_CMD_STORE_QUAD 4
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#define DBDMA_CMD_LOAD_QUAD 5
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#define DBDMA_CMD_NOP 6
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#define DBDMA_CMD_STOP 7
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/* Keys */
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#define DBDMA_KEY_STREAM0 0
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#define DBDMA_KEY_STREAM1 1
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#define DBDMA_KEY_STREAM2 2
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#define DBDMA_KEY_STREAM3 3
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/* value 4 is reserved */
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#define DBDMA_KEY_REGS 5
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#define DBDMA_KEY_SYSTEM 6
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#define DBDMA_KEY_DEVICE 7
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#define DBDMA_INT_NEVER 0
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#define DBDMA_INT_IF_TRUE 1
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#define DBDMA_INT_IF_FALSE 2
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#define DBDMA_INT_ALWAYS 3
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#define DBDMA_BRANCH_NEVER 0
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#define DBDMA_BRANCH_IF_TRUE 1
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#define DBDMA_BRANCH_IF_FALSE 2
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#define DBDMA_BRANCH_ALWAYS 3
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#define DBDMA_WAIT_NEVER 0
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#define DBDMA_WAIT_IF_TRUE 1
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#define DBDMA_WAIT_IF_FALSE 2
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#define DBDMA_WAIT_ALWAYS 3
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/* Channels */
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#define DBDMA_SCSI0 0x0
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#define DBDMA_CURIO_SCSI DBDMA_SCSI0
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#define DBDMA_FLOPPY 0x1
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#define DBDMA_ETHERNET_TX 0x2
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#define DBDMA_ETHERNET_RV 0x3
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#define DBDMA_SCC_XMIT_A 0x4
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#define DBDMA_SCC_RECV_A 0x5
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#define DBDMA_SCC_XMIT_B 0x6
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#define DBDMA_SCC_RECV_B 0x7
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#define DBDMA_AUDIO_OUT 0x8
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#define DBDMA_AUDIO_IN 0x9
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#define DBDMA_SCSI1 0xA
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/* Control register values (in little endian) */
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#define DBDMA_STATUS_MASK 0x000000ff /* Status Mask */
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#define DBDMA_CNTRL_BRANCH 0x00000100
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/* 0x200 reserved */
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#define DBDMA_CNTRL_ACTIVE 0x00000400
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#define DBDMA_CNTRL_DEAD 0x00000800
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#define DBDMA_CNTRL_WAKE 0x00001000
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#define DBDMA_CNTRL_FLUSH 0x00002000
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#define DBDMA_CNTRL_PAUSE 0x00004000
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#define DBDMA_CNTRL_RUN 0x00008000
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#define DBDMA_SET_CNTRL(x) ( ((x) | (x) << 16) )
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#define DBDMA_CLEAR_CNTRL(x) ( (x) << 16)
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#define DBDMA_REGMAP(channel) \
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(dbdma_regmap_t *)((v_u_char *) POWERMAC_IO(PCI_DMA_BASE_PHYS) \
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+ (channel << 8))
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/* This struct is layout in little endian format */
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struct dbdma_command {
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u_int16_t d_count;
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u_int16_t d_command;
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u_int32_t d_address;
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u_int32_t d_cmddep;
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u_int16_t d_resid;
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u_int16_t d_status;
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};
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typedef struct dbdma_command dbdma_command_t;
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#define DBDMA_BUILD_CMD(d, cmd, key, interrupt, wait, branch) { \
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dbdma_st16(&(d)->d_command, \
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((cmd) << 12) | ((key) << 8) | \
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((interrupt) << 4) | \
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((branch) << 2) | (wait)); \
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}
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#define DBDMA_BUILD(d, cmd, key, count, address, interrupt, wait, branch) { \
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dbdma_st16(&(d)->d_command, \
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((cmd) << 12) | ((key) << 8) | \
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((interrupt) << 4) | \
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((branch) << 2) | (wait)); \
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dbdma_st16(&(d)->d_count, count); \
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dbdma_st32(&(d)->d_address, address); \
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(d)->d_resid = 0; \
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(d)->d_status = 0; \
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(d)->d_cmddep = 0; \
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}
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static __inline__ void
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dbdma_st32(a, x)
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volatile u_int32_t *a;
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u_int32_t x;
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{
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__asm__ volatile
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("stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
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}
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static __inline__ void
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dbdma_st16(a, x)
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volatile u_int16_t *a;
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u_int16_t x;
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{
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__asm__ volatile
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("sthbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
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}
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static __inline__ u_int32_t
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dbdma_ld32(a)
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volatile u_int32_t *a;
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{
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u_int32_t swap;
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__asm__ volatile
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("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
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return swap;
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}
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static __inline__ u_int16_t
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dbdma_ld16(a)
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volatile u_int16_t *a;
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{
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u_int16_t swap;
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__asm__ volatile
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("lhbrx %0,0,%1" : "=r" (swap) : "r" (a));
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return swap;
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}
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#define DBDMA_LD4_ENDIAN(a) dbdma_ld32(a)
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#define DBDMA_ST4_ENDIAN(a, x) dbdma_st32(a, x)
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/*
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* DBDMA Channel layout
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*
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* NOTE - This structure is in little-endian format.
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*/
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struct dbdma_regmap {
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unsigned long d_control; /* Control Register */
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unsigned long d_status; /* DBDMA Status Register */
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unsigned long d_cmdptrhi; /* MSB of command pointer (not used yet) */
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unsigned long d_cmdptrlo; /* LSB of command pointer */
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unsigned long d_intselect; /* Interrupt Select */
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unsigned long d_branch; /* Branch selection */
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unsigned long d_wait; /* Wait selection */
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unsigned long d_transmode; /* Transfer modes */
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unsigned long d_dataptrhi; /* MSB of Data Pointer */
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unsigned long d_dataptrlo; /* LSB of Data Pointer */
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unsigned long d_reserved; /* Reserved for the moment */
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unsigned long d_branchptrhi; /* MSB of Branch Pointer */
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unsigned long d_branchptrlo; /* LSB of Branch Pointer */
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/* The remaining fields are undefinied and unimplemented */
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};
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typedef volatile struct dbdma_regmap dbdma_regmap_t;
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/* DBDMA routines */
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void dbdma_start(dbdma_regmap_t *channel, dbdma_command_t *commands);
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void dbdma_stop(dbdma_regmap_t *channel);
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void dbdma_flush(dbdma_regmap_t *channel);
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void dbdma_reset(dbdma_regmap_t *channel);
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void dbdma_continue(dbdma_regmap_t *channel);
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void dbdma_pause(dbdma_regmap_t *channel);
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dbdma_command_t *dbdma_alloc(int); /* Allocate command structures */
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#endif /* !defined(_POWERMAC_DBDMA_H_) */
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