468 lines
11 KiB
C
468 lines
11 KiB
C
/* $NetBSD: sdhc_pci.c,v 1.14 2017/04/27 10:01:54 msaitoh Exp $ */
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/* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.14 2017/04/27 10:01:54 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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#endif
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/pmf.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/sdmmc/sdhcreg.h>
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#include <dev/sdmmc/sdhcvar.h>
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#include <dev/sdmmc/sdmmcvar.h>
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/* PCI base address registers */
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#define SDHC_PCI_BAR_START PCI_MAPREG_START
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#define SDHC_PCI_BAR_END PCI_MAPREG_END
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/* PCI interface classes */
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#define SDHC_PCI_INTERFACE_NO_DMA 0x00
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#define SDHC_PCI_INTERFACE_DMA 0x01
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#define SDHC_PCI_INTERFACE_VENDOR 0x02
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/*
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* 8-bit PCI configuration register that tells us how many slots there
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* are and which BAR entry corresponds to the first slot.
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*/
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#define SDHC_PCI_CONF_SLOT_INFO 0x40
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#define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1)
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#define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7)
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struct sdhc_pci_softc {
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struct sdhc_softc sc;
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pci_chipset_tag_t sc_pc;
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void *sc_ih;
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};
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static int sdhc_pci_match(device_t, cfdata_t, void *);
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static void sdhc_pci_attach(device_t, device_t, void *);
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static int sdhc_pci_detach(device_t, int);
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CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc),
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sdhc_pci_match, sdhc_pci_attach, sdhc_pci_detach, NULL);
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#ifdef SDHC_DEBUG
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#define DPRINTF(s) printf s
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#else
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#define DPRINTF(s) /**/
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#endif
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static const struct sdhc_pci_quirk {
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pci_vendor_id_t vendor;
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pci_product_id_t product;
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pci_vendor_id_t subvendor;
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pci_product_id_t subproduct;
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u_int function;
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uint32_t flags;
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#define SDHC_PCI_QUIRK_FORCE_DMA __BIT(0)
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#define SDHC_PCI_QUIRK_TI_HACK __BIT(1)
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#define SDHC_PCI_QUIRK_NO_PWR0 __BIT(2)
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#define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK __BIT(3)
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#define SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK __BIT(4)
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#define SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET __BIT(5)
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} sdhc_pci_quirk_table[] = {
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{
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PCI_VENDOR_TI,
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PCI_PRODUCT_TI_PCI72111SD,
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0xffff,
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0xffff,
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4,
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SDHC_PCI_QUIRK_TI_HACK
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},
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{
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PCI_VENDOR_TI,
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PCI_PRODUCT_TI_PCIXX12SD,
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0xffff,
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0xffff,
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3,
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SDHC_PCI_QUIRK_TI_HACK
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},
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{
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PCI_VENDOR_ENE,
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PCI_PRODUCT_ENE_CB712,
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0xffff,
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0xffff,
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0,
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SDHC_PCI_QUIRK_NO_PWR0
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},
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{
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PCI_VENDOR_RICOH,
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PCI_PRODUCT_RICOH_Rx5U823,
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0xffff,
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0xffff,
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0,
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SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK
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},
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{
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PCI_VENDOR_RICOH,
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PCI_PRODUCT_RICOH_Rx5C822,
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0xffff,
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0xffff,
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~0,
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SDHC_PCI_QUIRK_FORCE_DMA
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},
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{
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PCI_VENDOR_RICOH,
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PCI_PRODUCT_RICOH_Rx5U822,
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0xffff,
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0xffff,
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~0,
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SDHC_PCI_QUIRK_FORCE_DMA
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},
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{
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PCI_VENDOR_INTEL,
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PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC,
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0xffff,
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0xffff,
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~0,
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SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
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},
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{
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PCI_VENDOR_INTEL,
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PCI_PRODUCT_INTEL_BSW_SSC_MMC,
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0xffff,
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0xffff,
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~0,
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SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
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},
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{
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PCI_VENDOR_INTEL,
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PCI_PRODUCT_INTEL_100SERIES_LP_EMMC,
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0xffff,
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0xffff,
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~0,
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SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
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},
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};
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static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *);
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static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *);
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static void sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *,
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struct sdhc_host *);
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static uint32_t
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sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa)
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{
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const struct sdhc_pci_quirk *q;
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pcireg_t id;
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pci_vendor_id_t vendor;
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pci_product_id_t product;
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int i;
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for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) {
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q = &sdhc_pci_quirk_table[i];
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if ((PCI_VENDOR(pa->pa_id) == q->vendor)
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&& (PCI_PRODUCT(pa->pa_id) == q->product)) {
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if ((q->function != ~0)
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&& (pa->pa_function != q->function))
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continue;
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if ((q->subvendor == 0xffff)
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&& (q->subproduct == 0xffff))
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return (q->flags);
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id = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCI_SUBSYS_ID_REG);
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vendor = PCI_VENDOR(id);
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product = PCI_PRODUCT(id);
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if ((q->subvendor != 0xffff)
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&& (q->subproduct != 0xffff)) {
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if ((vendor == q->subvendor)
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&& (product == q->subproduct))
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return (q->flags);
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} else if (q->subvendor != 0xffff) {
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if (product == q->subproduct)
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return (q->flags);
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} else {
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if (vendor == q->subvendor)
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return (q->flags);
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}
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}
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}
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return (0);
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}
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static int
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sdhc_pci_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC)
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return (1);
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
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(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823))
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return (1);
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return (0);
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}
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static void
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sdhc_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct sdhc_pci_softc *sc = device_private(self);
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struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t tag = pa->pa_tag;
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pci_intr_handle_t ih;
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pcireg_t csr;
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pcireg_t slotinfo;
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char const *intrstr;
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int nslots;
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int reg;
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int cnt;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_size_t size;
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uint32_t flags;
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char intrbuf[PCI_INTRSTR_LEN];
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sc->sc.sc_dev = self;
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sc->sc.sc_dmat = pa->pa_dmat;
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sc->sc.sc_host = NULL;
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sc->sc_pc = pc;
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pci_aprint_devinfo(pa, NULL);
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/* Some controllers needs special treatment. */
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flags = sdhc_pci_lookup_quirk_flags(pa);
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if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK))
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sdhc_pci_quirk_ti_hack(pa);
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if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA))
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SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA);
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if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0))
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SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0);
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if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK))
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sdhc_pci_quirk_ricoh_lower_freq_hack(pa);
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if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK))
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SET(sc->sc.sc_flags, SDHC_FLAG_SLOW_SDR50);
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if (ISSET(flags, SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET))
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sc->sc.sc_vendor_hw_reset = sdhc_pci_intel_emmc_hw_reset;
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/*
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* Map and attach all hosts supported by the host controller.
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*/
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slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO);
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nslots = SDHC_PCI_NUM_SLOTS(slotinfo);
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/* Allocate an array big enough to hold all the possible hosts */
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sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots,
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M_DEVBUF, M_NOWAIT | M_ZERO);
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if (sc->sc.sc_host == NULL) {
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aprint_error_dev(self, "couldn't alloc memory\n");
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goto err;
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}
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/* Enable the device. */
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE);
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/* Map and establish the interrupt. */
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if (pci_intr_map(pa, &ih)) {
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aprint_error_dev(self, "couldn't map interrupt\n");
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goto err;
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}
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intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
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sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_SDMMC, sdhc_intr,
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&sc->sc, device_xname(self));
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "couldn't establish interrupt\n");
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goto err;
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}
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aprint_normal_dev(self, "interrupting at %s\n", intrstr);
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/* Enable use of DMA if supported by the interface. */
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if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA))
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SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA);
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/* XXX: handle 64-bit BARs */
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cnt = 0;
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for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) *
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sizeof(uint32_t);
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reg < SDHC_PCI_BAR_END && nslots > 0;
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reg += sizeof(uint32_t), nslots--) {
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if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0,
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&iot, &ioh, NULL, &size)) {
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continue;
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}
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cnt++;
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if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) {
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/* XXX: sc->sc_host leak */
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aprint_error_dev(self,
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"couldn't initialize host (0x%x)\n", reg);
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}
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}
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if (cnt == 0) {
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aprint_error_dev(self, "couldn't map register\n");
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goto err;
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}
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if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume,
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sdhc_shutdown)) {
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aprint_error_dev(self, "couldn't establish powerhook\n");
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}
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return;
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err:
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if (sc->sc.sc_host != NULL) {
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free(sc->sc.sc_host, M_DEVBUF);
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sc->sc.sc_host = NULL;
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}
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}
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static int
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sdhc_pci_detach(device_t self, int flags)
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{
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struct sdhc_pci_softc * const sc = device_private(self);
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int rv;
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rv = sdhc_detach(&sc->sc, flags);
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if (rv)
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return rv;
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if (sc->sc_ih != NULL) {
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pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
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sc->sc_ih = NULL;
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}
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if (sc->sc.sc_host != NULL) {
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free(sc->sc.sc_host, M_DEVBUF);
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sc->sc.sc_host = NULL;
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}
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return rv;
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}
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static void
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sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val)
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{
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pcireg_t r;
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r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
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r &= ~(0xff << ((reg & 0x3) * 8));
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r |= (val << ((reg & 0x3) * 8));
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pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r);
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}
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/* TI specific register */
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#define SDHC_PCI_GENERAL_CTL 0x4c
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#define MMC_SD_DIS 0x02
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static void
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sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa)
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t tag;
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pcireg_t id, reg;
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/* Look at func - 1 for the flash device */
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tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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if (PCI_VENDOR(id) != PCI_VENDOR_TI) {
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return;
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}
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switch (PCI_PRODUCT(id)) {
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case PCI_PRODUCT_TI_PCI72111FM:
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case PCI_PRODUCT_TI_PCIXX12FM:
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break;
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default:
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return;
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}
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/*
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* Disable MMC/SD on the flash media controller so the
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* SD host takes over.
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*/
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reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL);
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reg |= MMC_SD_DIS;
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pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg);
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}
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/* Ricoh specific register */
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#define SDHC_PCI_MODE_KEY 0xf9
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#define SDHC_PCI_MODE 0x150
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#define SDHC_PCI_MODE_SD20 0x10
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#define SDHC_PCI_BASE_FREQ_KEY 0xfc
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#define SDHC_PCI_BASE_FREQ 0xe1
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/* Some RICOH controllers need to be bumped into the right mode. */
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static void
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sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa)
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{
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/* Enable SD2.0 mode. */
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc);
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20);
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00);
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/*
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* Some SD/MMC cards don't work with the default base
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* clock frequency of 200MHz. Lower it to 50Hz.
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*/
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01);
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50);
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00);
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printf("quirked\n");
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}
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static void
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sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *sc, struct sdhc_host *hp)
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{
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kmutex_t *plock = sdhc_host_lock(hp);
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uint8_t reg;
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mutex_enter(plock);
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reg = sdhc_host_read_1(hp, SDHC_POWER_CTL);
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reg |= 0x10;
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sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);
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sdmmc_delay(10);
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reg &= ~0x10;
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sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);
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sdmmc_delay(1000);
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mutex_exit(plock);
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}
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