275 lines
8.9 KiB
C
275 lines
8.9 KiB
C
/* $NetBSD: rdcide.c,v 1.8 2014/07/08 18:01:26 msaitoh Exp $ */
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/*
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* Copyright (c) 2011 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rdcide.c,v 1.8 2014/07/08 18:01:26 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/rdcide_reg.h>
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static void rdcide_chip_map(struct pciide_softc *,
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const struct pci_attach_args *);
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static void rdcide_setup_channel(struct ata_channel *);
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static bool rdcide_resume(device_t, const pmf_qual_t *);
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static bool rdcide_suspend(device_t, const pmf_qual_t *);
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static int rdcide_match(device_t, cfdata_t, void *);
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static void rdcide_attach(device_t, device_t, void *);
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static const struct pciide_product_desc pciide_intel_products[] = {
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{ PCI_PRODUCT_RDC_R1011_IDE,
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0,
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"RDC R1011 IDE controller",
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rdcide_chip_map,
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},
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{ PCI_PRODUCT_RDC_R1012_IDE,
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0,
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"RDC R1012 IDE controller",
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rdcide_chip_map,
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},
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};
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CFATTACH_DECL_NEW(rdcide, sizeof(struct pciide_softc),
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rdcide_match, rdcide_attach, NULL, NULL);
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static int
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rdcide_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC) {
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if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
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return (2);
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}
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return (0);
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}
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static void
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rdcide_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_intel_products));
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if (!pmf_device_register(self, rdcide_suspend, rdcide_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static bool
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rdcide_resume(device_t dv, const pmf_qual_t *qual)
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{
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struct pciide_softc *sc = device_private(dv);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR,
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sc->sc_pm_reg[0]);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR,
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sc->sc_pm_reg[1]);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR,
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sc->sc_pm_reg[2]);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR,
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sc->sc_pm_reg[3]);
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return true;
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}
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static bool
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rdcide_suspend(device_t dv, const pmf_qual_t *qual)
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{
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struct pciide_softc *sc = device_private(dv);
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sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag,
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RDCIDE_PATR);
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sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag,
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RDCIDE_PSD1ATR);
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sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag,
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RDCIDE_UDCCR);
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sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag,
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RDCIDE_IIOCR);
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return true;
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}
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static void
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rdcide_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int channel;
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u_int32_t patr;
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.dma_init = pciide_dma_init;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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sc->sc_wdcdev.sc_atac.atac_set_modes = rdcide_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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sc->sc_wdcdev.wdc_maxdrives = 2;
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ATADEBUG_PRINT(("rdcide_setup_chip: old PATR=0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", PSD1ATR=0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", UDCCR 0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", IIOCR 0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR);
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if ((patr & RDCIDE_PATR_EN(channel)) == 0) {
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aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"%s channel ignored (disabled)\n", cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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continue;
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}
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pciide_mapchan(pa, cp, interface, pciide_pci_intr);
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}
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ATADEBUG_PRINT(("rdcide_setup_chip: PATR=0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", PSD1ATR=0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", UDCCR 0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT((", IIOCR 0x%x",
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pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)),
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DEBUG_PROBE);
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ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
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}
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static void
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rdcide_setup_channel(struct ata_channel *chp)
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{
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u_int8_t drive;
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u_int32_t patr, psd1atr, udccr, iiocr;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
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patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR);
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psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR);
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udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR);
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iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR);
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/* setup DMA */
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pciide_channel_dma_setup(cp);
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/* clear modes */
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patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1));
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psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->ch_channel);
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psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->ch_channel);
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for (drive = 0; drive < 2; drive++) {
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udccr &= ~RDCIDE_UDCCR_EN(chp->ch_channel, drive);
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udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->ch_channel, drive);
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iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->ch_channel, drive);
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}
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/* now setup modes */
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for (drive = 0; drive < 2; drive++) {
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if (drvp[drive].drive_type == ATA_DRIVET_NONE)
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continue;
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if (drvp[drive].drive_type == ATA_DRIVET_ATAPI)
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patr |= RDCIDE_PATR_ATA(chp->ch_channel, drive);
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if (drive == 0) {
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patr |= RDCIDE_PATR_SETUP(
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rdcide_setup[drvp[drive].PIO_mode],
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chp->ch_channel);
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patr |= RDCIDE_PATR_HOLD(
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rdcide_hold[drvp[drive].PIO_mode],
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chp->ch_channel);
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} else {
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patr |= RDCIDE_PATR_DEV1_TEN(chp->ch_channel);
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psd1atr |= RDCIDE_PSD1ATR_SETUP(
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rdcide_setup[drvp[drive].PIO_mode],
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chp->ch_channel);
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psd1atr |= RDCIDE_PSD1ATR_HOLD(
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rdcide_hold[drvp[drive].PIO_mode],
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chp->ch_channel);
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}
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if (drvp[drive].PIO_mode > 0) {
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patr |= RDCIDE_PATR_FTIM(chp->ch_channel, drive);
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patr |= RDCIDE_PATR_IORDY(chp->ch_channel, drive);
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}
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if (drvp[drive].drive_flags & ATA_DRIVE_DMA) {
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patr |= RDCIDE_PATR_DMAEN(chp->ch_channel, drive);
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}
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if ((drvp[drive].drive_flags & ATA_DRIVE_UDMA) == 0)
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continue;
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if ((iiocr & RDCIDE_IIOCR_CABLE(chp->ch_channel, drive)) == 0
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&& drvp[drive].UDMA_mode > 2)
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drvp[drive].UDMA_mode = 2;
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udccr |= RDCIDE_UDCCR_EN(chp->ch_channel, drive);
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udccr |= RDCIDE_UDCCR_TIM(
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rdcide_udmatim[drvp[drive].UDMA_mode],
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chp->ch_channel, drive);
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iiocr |= RDCIDE_IIOCR_CLK(
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rdcide_udmaclk[drvp[drive].UDMA_mode],
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chp->ch_channel, drive);
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}
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr);
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pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr);
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}
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