119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
/* $NetBSD: cx23885reg.h,v 1.2 2011/08/09 11:26:40 jmcneill Exp $ */
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/*
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* Copyright (c) 2008, 2011 Jonathan A. Kollasch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_CX23885REG_H
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#define _DEV_PCI_CX23885REG_H
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#include <dev/pci/pcireg.h>
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#define CX23885_MMBASE PCI_BAR(0)
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/* misc. registers */
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#define DEV_CNTRL2 0x040000
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#define PCI_INT_MSK 0x040010
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#define PCI_INT_STAT 0x040014
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#define PCI_INT_MSTAT 0x040018
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#define VID_C_INT_MSK 0x040040
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#define VID_C_INT_STAT 0x040044
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#define VID_C_INT_MSTAT 0x040048
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#define VID_C_INT_SSTAT 0x04004c
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#define DMA5_PTR1 0x100010
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#define DMA5_PTR2 0x100050
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#define DMA5_CNT1 0x100090
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#define DMA5_CNT2 0x1000d0
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/* GPIO */
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#define GP0_IO 0x110010
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#define GPIO_ISM 0x110014
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#define SOFT_RESET 0x11001c
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#define CLK_DELAY 0x110048
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#define PAD_CTRL 0x11004c
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/* Video C Interface */
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#define VID_C_GPCNT 0x130220
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#define VID_C_GPCNT_CTL 0x130230
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#define VBI_C_GPCNT_CTL 0x130234
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#define VID_C_DMA_CTL 0x130240
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#define VID_C_LNGTH 0x130250
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#define VID_C_HW_SOP_CTL 0x130254
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#define VID_C_GEN_CTL 0x130258
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#define VID_C_BD_PKT_STATUS 0x13025c
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#define VID_C_SOP_STATUS 0x130260
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#define VID_C_FIFO_OVFL_STAT 0x130264
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#define VID_C_VLD_MISC 0x130268
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#define VID_C_TS_CLK_EN 0x13026c
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/* serial controllers */
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#define I2C_BASE 0x180000
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#define I2C_SIZE 0x010000
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#define I2C_NUM 3
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/* RISC instructions */
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#define CX_RISC_WRITECR 0xd0000000
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#define CX_RISC_WRITECM 0xc0000000
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#define CX_RISC_WRITERM 0xb0000000
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#define CX_RISC_READC 0xa0000000
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#define CX_RISC_READ 0x90000000
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#define CX_RISC_SYNC 0x80000000
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#define CX_RISC_JUMP 0x70000000
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#define CX_RISC_WRITEC 0x50000000
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#define CX_RISC_SKIP 0x20000000
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#define CX_RISC_WRITE 0x10000000
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#define CX_RISC_SOL 0x08000000
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#define CX_RISC_EOL 0x04000000
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#define CX_RISC_IRQ2 0x02000000
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#define CX_RISC_IRQ1 0x01000000
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#define CX_RISC_IMM 0x00000001
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#define CX_RISC_SRP 0x00000001
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#define CX_CNT_CTL_NOOP 0x0
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#define CX_CNT_CTL_INCR 0x1
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#define CX_CNT_CTL_ZERO 0x3
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#define CX_RISC_CNT_CTL __BITS(17,16)
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#define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP)
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#define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR)
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#define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO)
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/* Channel Management Data Structure */
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/* offsets */
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#define CMDS_O_IRPC 0x00
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#define CMDS_O_CDTB 0x08
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#define CMDS_O_CDTS 0x0c
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#define CMDS_O_IQB 0x10
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#define CMDS_O_IQS 0x14
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/* bits */
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#define CMDS_IQS_ISRP __BIT(31)
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#endif /* !_DEV_PCI_CX23885REG_H */
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