420 lines
20 KiB
C
420 lines
20 KiB
C
/* $NetBSD: ctlreg.h,v 1.22 2000/05/05 11:07:15 pk Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ctlreg.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun4m support by Aaron Brown, Harvard University.
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* Changes Copyright (c) 1995 The President and Fellows of Harvard College.
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* All rights reserved.
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*/
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/*
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* Sun 4, 4c, and 4m control registers. (includes address space definitions
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* and some registers in control space).
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*/
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/*
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* The Alternate address spaces.
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*/
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/* 0x00 unused */
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/* 0x01 unused */
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#define ASI_CONTROL 0x02 /* cache enable, context reg, etc */
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#define ASI_SEGMAP 0x03 /* [4/4c] segment maps */
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#define ASI_SRMMUFP 0x03 /* [4m] ref mmu flush/probe */
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#define ASI_PTE 0x04 /* [4/4c] PTE space (pmegs) */
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#define ASI_SRMMU 0x04 /* [4m] ref mmu registers */
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#define ASI_REGMAP 0x06 /* [4/3-level MMU ] region maps */
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#define ASI_HWFLUSHSEG 0x05 /* [4/4c] hardware assisted version of FLUSHSEG */
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#define ASI_HWFLUSHPG 0x06 /* [4/4c] hardware assisted version of FLUSHPG */
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#define ASI_SRMMUDIAG 0x06 /* [4m] */
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#define ASI_HWFLUSHCTX 0x07 /* [4/4c] hardware assisted version of FLUSHCTX */
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#define ASI_USERI 0x08 /* I-space (user) */
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#define ASI_KERNELI 0x09 /* I-space (kernel) */
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#define ASI_USERD 0x0a /* D-space (user) */
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#define ASI_KERNELD 0x0b /* D-space (kernel) */
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#define ASI_FLUSHREG 0x7 /* [4/4c] flush cache by region */
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#define ASI_FLUSHSEG 0x0c /* [4/4c] flush cache by segment */
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#define ASI_FLUSHPG 0x0d /* [4/4c] flush cache by page */
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#define ASI_FLUSHCTX 0x0e /* [4/4c] flush cache by context */
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#define ASI_DCACHE 0x0f /* [4] flush data cache */
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#define ASI_ICACHETAG 0x0c /* [4m] instruction cache tag */
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#define ASI_ICACHEDATA 0x0d /* [4m] instruction cache data */
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#define ASI_DCACHETAG 0x0e /* [4m] data cache tag */
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#define ASI_DCACHEDATA 0x0f /* [4m] data cache data */
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#define ASI_IDCACHELFP 0x10 /* [4m] flush i&d cache line (page) */
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#define ASI_IDCACHELFS 0x11 /* [4m] flush i&d cache line (seg) */
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#define ASI_IDCACHELFR 0x12 /* [4m] flush i&d cache line (reg) */
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#define ASI_IDCACHELFC 0x13 /* [4m] flush i&d cache line (ctxt) */
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#define ASI_IDCACHELFU 0x14 /* [4m] flush i&d cache line (user) */
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#define ASI_BLOCKCOPY 0x17 /* [4m] hypersparc: hardware block copy */
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#define ASI_BLOCKFILL 0x1f /* [4m] hypersparc: hardware block fill */
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#define ASI_BYPASS 0x20 /* [4m] sun ref mmu bypass,
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ie. direct phys access */
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#define ASI_HICACHECLR 0x31 /* [4m] hypersparc only: I-cache flash clear */
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#define ASI_ICACHECLR 0x36 /* [4m] ms1 only: I-cache flash clear */
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#define ASI_DCACHECLR 0x37 /* [4m] ms1 only: D-cache flash clear */
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#define ASI_DCACHEDIAG 0x39 /* [4m] data cache diagnostic register access */
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/*
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* [4/4c] Registers in the control space (ASI_CONTROL).
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*/
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#define AC_IDPROM 0x00000000 /* [4] ID PROM */
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#define AC_CONTEXT 0x30000000 /* [4/4c] context register (byte) */
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#define AC_SYSENABLE 0x40000000 /* [4/4c] system enable register (byte) */
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#define AC_DVMA_ENABLE 0x50000000 /* [4] enable user dvma */
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#define AC_BUS_ERR 0x60000000 /* [4] bus error register */
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#define AC_SYNC_ERR 0x60000000 /* [4c] sync (memory) error reg */
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#define AC_SYNC_VA 0x60000004 /* [4c] sync error virtual addr */
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#define AC_ASYNC_ERR 0x60000008 /* [4c] async error reg */
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#define AC_ASYNC_VA 0x6000000c /* [4c] async error virtual addr */
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#define AC_DIAG_REG 0x70000000 /* [4] diagnostic reg */
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#define AC_CACHETAGS 0x80000000 /* [4/4c?] cache tag base address */
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#define AC_CACHEDATA 0x90000000 /* [4] cached data [sun4/400?] */
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#define AC_DVMA_MAP 0xd0000000 /* [4] user dvma map entries */
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#define AC_VMEINTVEC 0xe0000000 /* [4] vme interrupt vector */
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#define AC_SERIAL 0xf0000000 /* [4/4c] special serial port sneakiness */
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/* AC_SERIAL is not used in the kernel (it is for the PROM) */
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/* XXX: does not belong here */
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#define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */
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/*
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* [4/4c]
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* Bits in sync error register. Reading the register clears these;
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* otherwise they accumulate. The error(s) occurred at the virtual
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* address stored in the sync error address register, and may have
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* been due to, e.g., what would usually be called a page fault.
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* Worse, the bits accumulate during instruction prefetch, so
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* various bits can be on that should be off.
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*/
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#define SER_WRITE 0x8000 /* error occurred during write */
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#define SER_INVAL 0x80 /* PTE had PG_V off */
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#define SER_PROT 0x40 /* operation violated PTE prot */
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#define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */
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#define SER_SBUSERR 0x10 /* S-Bus bus error */
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#define SER_MEMERR 0x08 /* memory ecc/parity error */
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#define SER_SZERR 0x02 /* [4/vme?] size error, whatever that is */
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#define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */
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#define SER_BITS \
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"\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG"
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/*
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* [4/4c]
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* Bits in async error register (errors from DVMA or Sun-4 cache
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* writeback). The corresponding bit is also set in the sync error reg.
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*
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* A writeback invalid error means there is a bug in the PTE manager.
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*
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* The word is that the async error register does not work right.
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*/
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#define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */
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#define AER_TIMEOUT 0x20 /* bus timeout */
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#define AER_DVMAERR 0x10 /* bus error during DVMA */
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#define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR"
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/*
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* [4/4c] Bits in system enable register.
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*/
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#define SYSEN_DVMA 0x20 /* Enable dvma */
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#define SYSEN_CACHE 0x10 /* Enable cache */
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#define SYSEN_IOCACHE 0x40 /* Enable IO cache */
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#define SYSEN_VIDEO 0x08 /* Enable on-board video */
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#define SYSEN_RESET 0x04 /* Reset the hardware */
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#define SYSEN_RESETVME 0x02 /* Reset the VME bus */
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/*
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* [4m] Bits in ASI_CONTROL space, sun4m only.
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*/
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#define MXCC_STREAM_DATA 0x1c00000 /* Stream data register */
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#define MXCC_STREAM_SRC 0x1c00100 /* Stream source register */
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#define MXCC_STREAM_DST 0x1c00200 /* Stream dest register */
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#define MXCC_CTRLREG 0x1c00a00 /* Control register for MXCC */
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/* Bits in MXCC_CTRLREG */
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#define MXCC_CTRLREG_HC 0x1 /* Half cache (Xbus only) */
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#define MXCC_CTRLREG_CS 0x2 /* E-cache size (Xbus only) */
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#define MXCC_CTRLREG_CE 0x4 /* Enable e-cache */
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#define MXCC_CTRLREG_PE 0x8 /* Parity enable */
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#define MXCC_CTRLREG_MC 0x10 /* Multiple command enable */
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#define MXCC_CTRLREG_PF 0x20 /* Prefetch enable */
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#define MXCC_CTRLREG_WI 0x40 /* Write invalidate (Xbus only) */
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#define MXCC_CTRLREG_BWC_MASK 0x180 /* Bus watch count (Xbus only) */
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#define MXCC_CTRLREG_RC 0x200 /* Read reference count */
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/*
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* Stream register usage:
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* To fill a block with some value, load that value into the 64 byte
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* stream data register (using double-word access; on Mbus only the
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* lower 32 bytes are used), then write the physical address of
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* the destination into the stream destination register.
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*
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* To copy a block, write the physical address of the source into
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* the stream source register causing the block to be transferred
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* into the stream data register, then write the physical address of
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* the destination into the stream destination register.
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*
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* In both cases, or in the MXCC_STREAM_CE bit to make the transactions
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* cache-coherent. Note that stream operations do not cause cache
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* lines to be allocated.
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*/
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#define MXCC_STREAM_BLKSZ 32 /* Unit for stream ops */
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#define MXCC_STREAM_C 0x1000000000ULL /* Cacheable bit for stream ops */
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/*
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* Bits in ASI_SRMMUFP space.
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* Bits 8-11 determine the type of flush/probe.
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* Address bits 12-31 hold the page frame.
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*/
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#define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */
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#define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/
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#define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */
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/*
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* [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU).
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*/
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#define SRMMU_PCR 0x00000000 /* Processor control register */
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#define SRMMU_CXTPTR 0x00000100 /* Context table pointer register */
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#define SRMMU_CXR 0x00000200 /* Context register */
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#define SRMMU_SFSR 0x00000300 /* Synchronous fault status reg */
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#define SRMMU_SFAR 0x00000400 /* Synchronous fault address reg */
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#define SRMMU_AFSR 0x00000500 /* Asynchronous fault status reg (HS) */
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#define SRMMU_AFAR 0x00000600 /* Asynchronous fault address reg (HS)*/
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#define SRMMU_PCFG 0x00000600 /* Processor configuration reg (TURBO)*/
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#define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */
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/*
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* [4m] Bits in SRMMU control register. One set per module.
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*/
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#define VIKING_PCR_ME 0x00000001 /* MMU Enable */
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#define VIKING_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define VIKING_PCR_PSO 0x00000080 /* Partial Store Ordering enable */
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#define VIKING_PCR_DCE 0x00000100 /* Data cache enable bit */
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#define VIKING_PCR_ICE 0x00000200 /* SuperSPARC instr. cache enable */
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#define VIKING_PCR_SB 0x00000400 /* Store buffer enable bit */
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#define VIKING_PCR_MB 0x00000800 /* MBus mode: 0=MXCC, 1=no MXCC */
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#define VIKING_PCR_PE 0x00001000 /* Enable memory parity checking */
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#define VIKING_PCR_BM 0x00002000 /* 1 iff booting */
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#define VIKING_PCR_SE 0x00004000 /* Coherent bus snoop enable */
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#define VIKING_PCR_AC 0x00008000 /* 1=cache non-MMU accesses */
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#define VIKING_PCR_TC 0x00010000 /* 1=cache table walks */
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#define HYPERSPARC_PCR_ME 0x00000001 /* MMU Enable */
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#define HYPERSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define HYPERSPARC_PCR_CE 0x00000100 /* Cache enable bit */
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#define HYPERSPARC_PCR_CM 0x00000400 /* Cache mode: 1=write-back */
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#define HYPERSPARC_PCR_MR 0x00000800 /* Memory reflection: 1 = on */
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#define HYPERSPARC_PCR_CS 0x00001000 /* cache size: 1=256k, 0=128k */
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#define HYPERSPARC_PCR_C 0x00002000 /* enable cache when MMU off */
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#define HYPERSPARC_PCR_BM 0x00004000 /* 1 iff booting */
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#define HYPERSPARC_PCR_MID 0x00078000 /* MBus module ID MID<3:0> */
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#define HYPERSPARC_PCR_WBE 0x00080000 /* Write buffer enable */
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#define HYPERSPARC_PCR_SE 0x00100000 /* Coherent bus snoop enable */
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#define HYPERSPARC_PCR_CWR 0x00200000 /* Cache wrap enable */
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#define CYPRESS_PCR_ME 0x00000001 /* MMU Enable */
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#define CYPRESS_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define CYPRESS_PCR_CE 0x00000100 /* Cache enable bit */
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#define CYPRESS_PCR_CL 0x00000200 /* Cache Lock (604 only) */
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#define CYPRESS_PCR_CM 0x00000400 /* Cache mode: 1=write-back */
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#define CYPRESS_PCR_MR 0x00000800 /* Memory reflection: 1=on (605 only) */
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#define CYPRESS_PCR_C 0x00002000 /* enable cache when MMU off */
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#define CYPRESS_PCR_BM 0x00004000 /* 1 iff booting */
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#define CYPRESS_PCR_MID 0x00078000 /* MBus module ID MID<3:0> (605 only) */
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#define CYPRESS_PCR_MV 0x00080000 /* Multichip Valid */
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#define CYPRESS_PCR_MCM 0x00300000 /* Multichip Mask */
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#define CYPRESS_PCR_MCA 0x00c00000 /* Multichip Address */
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#define MS1_PCR_ME 0x00000001 /* MMU Enable */
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#define MS1_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define MS1_PCR_DCE 0x00000100 /* Data cache enable */
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#define MS1_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define MS1_PCR_RC 0x00000c00 /* DRAM Refresh control */
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#define MS1_PCR_PE 0x00001000 /* Enable memory parity checking */
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#define MS1_PCR_BM 0x00004000 /* 1 iff booting */
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#define MS1_PCR_AC 0x00008000 /* 1=cache if ME==0 (and [ID]CE on) */
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#define MS1_PCR_ID 0x00010000 /* 1=disable ITBR */
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#define MS1_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */
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#define MS1_PCR_MV 0x00100000 /* Memory data View (diag) */
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#define MS1_PCR_DV 0x00200000 /* Data View (diag) */
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#define MS1_PCR_AV 0x00400000 /* Address View (diag) */
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#define MS1_PCR_STW 0x00800000 /* Software Tablewalk enable */
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#define SWIFT_PCR_ME 0x00000001 /* MMU Enable */
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#define SWIFT_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define SWIFT_PCR_DCE 0x00000100 /* Data cache enable */
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#define SWIFT_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define SWIFT_PCR_RC 0x00003c00 /* DRAM Refresh control */
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#define SWIFT_PCR_BM 0x00004000 /* 1 iff booting */
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#define SWIFT_PCR_AC 0x00008000 /* 1=cache if ME=0 (and [ID]CE on) */
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#define SWIFT_PCR_PA 0x00010000 /* TCX/SX control */
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#define SWIFT_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */
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#define SWIFT_PCR_PE 0x00040000 /* Enable memory parity checking */
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#define SWIFT_PCR_PMC 0x00180000 /* Page mode control */
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#define SWIFT_PCR_BF 0x00200000 /* Branch Folding */
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#define SWIFT_PCR_WP 0x00400000 /* Watch point enable */
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#define SWIFT_PCR_STW 0x00800000 /* Software Tablewalk enable */
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#define TURBOSPARC_PCR_ME 0x00000001 /* MMU Enable */
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#define TURBOSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define TURBOSPARC_PCR_ICS 0x00000004 /* I-cache snoop enable */
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#define TURBOSPARC_PCR_PSO 0x00000008 /* Partial Store order (ro!) */
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#define TURBOSPARC_PCR_DCE 0x00000100 /* Data cache enable */
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#define TURBOSPARC_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define TURBOSPARC_PCR_RC 0x00003c00 /* DRAM Refresh control */
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#define TURBOSPARC_PCR_BM 0x00004000 /* 1 iff booting */
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#define TURBOSPARC_PCR_PC 0x00020000 /* Parity ctrl: 0=even,1=odd */
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#define TURBOSPARC_PCR_PE 0x00040000 /* Enable parity checking */
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#define TURBOSPARC_PCR_PMC 0x00180000 /* Page mode control */
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/* The Turbosparc's Processor Configuration Register */
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#define TURBOSPARC_PCFG_SCC 0x00000007 /* e-cache config */
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#define TURBOSPARC_PCFG_SE 0x00000008 /* e-cache enable */
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#define TURBOSPARC_PCFG_US2 0x00000010 /* microsparc II compat */
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#define TURBOSPARC_PCFG_WT 0x00000020 /* write-through enable */
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#define TURBOSPARC_PCFG_SBC 0x000000c0 /* SBus Clock */
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#define TURBOSPARC_PCFG_WS 0x03800000 /* DRAM wait states */
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#define TURBOSPARC_PCFG_RAH 0x0c000000 /* DRAM Row Address Hold */
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#define TURBOSPARC_PCFG_AXC 0x30000000 /* AFX Clock */
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#define TURBOSPARC_PCFG_SNP 0x40000000 /* DVMA Snoop enable */
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#define TURBOSPARC_PCFG_IOCLK 0x80000000 /* I/O clock ratio */
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/* Implementation and Version fields are common to all modules */
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#define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */
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#define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */
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/* [4m] Bits in the Synchronous Fault Status Register */
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#define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */
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#define SFSR_CS 0x00010000 /* Control Space error */
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#define SFSR_SB 0x00008000 /* SS: Store Buffer Error */
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#define SFSR_PERR 0x00006000 /* Parity error code */
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#define SFSR_P 0x00004000 /* SS: Parity error */
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#define SFSR_UC 0x00001000 /* Uncorrectable error */
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#define SFSR_TO 0x00000800 /* S-Bus timeout */
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#define SFSR_BE 0x00000400 /* S-Bus bus error */
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#define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */
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#define SFSR_AT 0x000000e0 /* Access type */
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#define SFSR_FT 0x0000001c /* Fault type */
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#define SFSR_FAV 0x00000002 /* Fault Address is valid */
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#define SFSR_OW 0x00000001 /* Overwritten with new fault */
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#define SFSR_BITS "\177\020" \
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"b\21EM\0b\20CS\0b\17SB\0f\15\2PERR\0" \
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"b\14UC\0b\13TO\0b\12BE\0f\10\2LVL\0" \
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"f\05\3AT\0f\02\3FT\0b\01FAV\0b\01OW"
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/* [4m] Synchronous Fault Types */
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#define SFSR_FT_NONE (0 << 2) /* no fault */
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#define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */
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#define SFSR_FT_PROTERR (2 << 2) /* protection fault */
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#define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */
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#define SFSR_FT_TRANSERR (4 << 2) /* translation fault */
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#define SFSR_FT_BUSERR (5 << 2) /* access bus error */
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#define SFSR_FT_INTERR (6 << 2) /* internal error */
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#define SFSR_FT_RESERVED (7 << 2) /* reserved */
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/* [4m] Synchronous Fault Access Types */
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#define SFSR_AT_LDUDATA (0 << 5) /* Load user data */
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#define SFSR_AT_LDSDATA (1 << 5) /* Load supervisor data */
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#define SFSR_AT_LDUTEXT (2 << 5) /* Load user text */
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#define SFSR_AT_LDSTEXT (3 << 5) /* Load supervisor text */
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#define SFSR_AT_STUDATA (4 << 5) /* Store user data */
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#define SFSR_AT_STSDATA (5 << 5) /* Store supervisor data */
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#define SFSR_AT_STUTEXT (6 << 5) /* Store user text */
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#define SFSR_AT_STSTEXT (7 << 5) /* Store supervisor text */
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#define SFSR_AT_SUPERVISOR (1 << 5) /* Set iff supervisor */
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#define SFSR_AT_TEXT (2 << 5) /* Set iff text */
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#define SFSR_AT_STORE (4 << 5) /* Set iff store */
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/* [4m] Synchronous Fault PT Levels */
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#define SFSR_LVL_0 (0 << 8) /* Context table entry */
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#define SFSR_LVL_1 (1 << 8) /* Region table entry */
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#define SFSR_LVL_2 (2 << 8) /* Segment table entry */
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#define SFSR_LVL_3 (3 << 8) /* Page table entry */
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/* [4m] Asynchronous Fault Status Register bits */
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#define AFSR_AFO 0x00000001 /* Async. fault occurred */
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#define AFSR_AFA 0x000000f0 /* Bits <35:32> of faulting phys addr */
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#define AFSR_AFA_RSHIFT 4 /* Shift to get AFA to bit 0 */
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#define AFSR_AFA_LSHIFT 28 /* Shift to get AFA to bit 32 */
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#define AFSR_BE 0x00000400 /* Bus error */
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#define AFSR_TO 0x00000800 /* Bus timeout */
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#define AFSR_UC 0x00001000 /* Uncorrectable error */
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#define AFSR_SE 0x00002000 /* System error */
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#define AFSR_BITS "\177\020" \
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"b\15SE\0b\14UC\0b\13TO\0b\12BE\0f\04\4AFA\0b\0AFO\0"
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/* [4m] TLB Replacement Control Register bits */
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#define TLBC_DISABLE 0x00000020 /* Disable replacement counter */
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#define TLBC_RCNTMASK 0x0000001f /* Replacement counter (0-31) */
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/*
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* The Ross Hypersparc has an Instruction Cache Control Register (ICCR)
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* It contains an enable bit for the on-chip instruction cache and a bit
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* that controls whether a FLUSH instruction causes an Unimplemented
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* Flush Trap or just flushes the appropriate instruction cache line.
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* The ICCR register is implemented as Ancillary State register number 31.
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*/
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#define HYPERSPARC_ICCR_ICE 1 /* Instruction cache enable */
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#define HYPERSPARC_ICCR_FTD 2 /* Unimpl. flush trap disable */
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#define HYPERSPARC_ASRNUM_ICCR 31 /* ICCR == ASR#31 */
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