163 lines
5.4 KiB
C
163 lines
5.4 KiB
C
/* $NetBSD: tgavar.h,v 1.18 2009/05/18 00:14:27 he Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <dev/ic/ramdac.h>
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#include <dev/pci/tgareg.h>
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#include <dev/wscons/wsconsio.h>
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#include <dev/wscons/wscons_raster.h>
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#include <dev/wscons/wsdisplayvar.h>
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#include <dev/rasops/rasops.h>
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struct tga_devconfig;
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struct fbcmap;
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struct fbcursor;
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struct fbcurpos;
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struct tga_conf {
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const char *tgac_name; /* name for this board type */
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struct ramdac_funcs *(*ramdac_funcs)(void);
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int tgac_phys_depth; /* physical frame buffer depth */
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vsize_t tgac_cspace_size; /* core space size */
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vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */
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int tgac_ndbuf; /* number of display buffers */
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vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */
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vsize_t tgac_dbufsz[2]; /* display buffer sizes */
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int tgac_nbbuf; /* number of display buffers */
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vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */
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vsize_t tgac_bbufsz[2]; /* back buffer sizes */
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};
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struct tga_devconfig {
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bus_space_tag_t dc_memt;
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bus_space_handle_t dc_memh;
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pci_chipset_tag_t dc_pc; /* PCI chipset tag */
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pcitag_t dc_pcitag; /* PCI tag */
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bus_addr_t dc_pcipaddr; /* PCI phys addr. */
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bus_space_handle_t dc_regs; /* registers; XXX: need aliases */
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int dc_tga_type; /* the device type; see below */
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int dc_tga2; /* True if it is a TGA2 */
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const struct tga_conf *dc_tgaconf; /* device buffer configuration */
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struct ramdac_funcs
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*dc_ramdac_funcs; /* The RAMDAC functions */
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struct ramdac_cookie
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*dc_ramdac_cookie; /* the RAMDAC type; see above */
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vaddr_t dc_vaddr; /* memory space virtual base address */
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int dc_wid; /* width of frame buffer */
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int dc_ht; /* height of frame buffer */
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int dc_rowbytes; /* bytes in a FB scan line */
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vaddr_t dc_videobase; /* base of flat frame buffer */
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struct rasops_info dc_rinfo; /* raster display data */
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int dc_blanked; /* currently had video disabled */
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void *dc_ramdac_private; /* RAMDAC private storage */
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void (*dc_ramdac_intr)(void *);
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int dc_intrenabled; /* can we depend on interrupts yet? */
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};
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struct tga_softc {
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device_t sc_dev;
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struct tga_devconfig *sc_dc; /* device configuration */
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void *sc_intr; /* interrupt handler info */
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/* XXX should record intr fns/arg */
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int nscreens;
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};
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#define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */
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#define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */
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#define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */
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#define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */
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#define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */
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#define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */
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#define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */
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#define TGA_TYPE_POWERSTORM_4D20 7 /* unknown */
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#define TGA_TYPE_UNKNOWN 8 /* unknown */
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#define DEVICE_IS_TGA(class, id) \
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(((PCI_VENDOR(id) == PCI_VENDOR_DEC && \
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PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \
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PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0)
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int tga_cnmatch(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, pcitag_t);
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int tga_cnattach(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
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int, int, int);
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int tga_identify(struct tga_devconfig *);
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const struct tga_conf *tga_getconf(int);
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int tga_builtin_set_cursor(struct tga_devconfig *, struct wsdisplay_cursor *);
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int tga_builtin_get_cursor(struct tga_devconfig *, struct wsdisplay_cursor *);
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int tga_builtin_set_curpos(struct tga_devconfig *, struct wsdisplay_curpos *);
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int tga_builtin_get_curpos(struct tga_devconfig *, struct wsdisplay_curpos *);
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int tga_builtin_get_curmax(struct tga_devconfig *, struct wsdisplay_curpos *);
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/* Read a TGA register */
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#define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
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(reg) << 2))
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/* Write a TGA register */
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#define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
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(reg) << 2, (val))
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/* Write a TGA register at an alternate aliased location */
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#define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
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(dc)->dc_memt, (dc)->dc_regs, \
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((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \
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(val))
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/* Insert a write barrier */
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#define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
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(dc)->dc_memt, (dc)->dc_regs, \
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((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)
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/* Insert a read barrier */
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#define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
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(dc)->dc_memt, (dc)->dc_regs, \
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((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)
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/* Insert a read/write barrier */
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#define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
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(dc)->dc_memt, (dc)->dc_regs, \
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((reg) << 2), 4 * (nregs), \
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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