620 lines
16 KiB
C
620 lines
16 KiB
C
/* $NetBSD: igma.c,v 1.4 2019/12/22 23:23:32 thorpej Exp $ */
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/*
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* Copyright (c) 2014 Michael van Elst
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Intel Graphic Media Accelerator
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: igma.c,v 1.4 2019/12/22 23:23:32 thorpej Exp $");
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#include "vga.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciio.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/i2c_bitbang.h>
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#include <dev/i2c/ddcvar.h>
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#include <dev/videomode/videomode.h>
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#include <dev/videomode/edidvar.h>
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#include <dev/wscons/wsdisplayvar.h>
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#if NVGA > 0
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#include <dev/ic/mc6845reg.h>
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#include <dev/ic/pcdisplayvar.h>
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#include <dev/ic/vgareg.h>
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#include <dev/ic/vgavar.h>
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#endif
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#include <dev/pci/igmareg.h>
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#include <dev/pci/igmavar.h>
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#include "igmafb.h"
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struct igma_softc;
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struct igma_i2c {
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struct igma_softc *ii_sc;
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bus_addr_t ii_reg;
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struct i2c_controller ii_i2c;
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const char *ii_name;
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u_int32_t ii_dir;
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};
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struct igma_softc {
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device_t sc_dev;
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struct igma_chip sc_chip;
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struct igma_i2c sc_ii[GMBUS_NUM_PORTS];
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};
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static int igma_match(device_t, cfdata_t, void *);
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static void igma_attach(device_t, device_t, void *);
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static int igma_print(void *, const char *);
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static void igma_i2c_attach(struct igma_softc *);
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CFATTACH_DECL_NEW(igma, sizeof(struct igma_softc),
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igma_match, igma_attach, NULL, NULL);
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static int igma_i2c_acquire_bus(void *, int);
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static void igma_i2c_release_bus(void *, int);
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static int igma_i2c_send_start(void *, int);
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static int igma_i2c_send_stop(void *, int);
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static int igma_i2c_initiate_xfer(void *, i2c_addr_t, int);
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static int igma_i2c_read_byte(void *, uint8_t *, int);
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static int igma_i2c_write_byte(void *, uint8_t, int);
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static void igma_i2cbb_set_bits(void *, uint32_t);
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static void igma_i2cbb_set_dir(void *, uint32_t);
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static uint32_t igma_i2cbb_read(void *);
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static void igma_reg_barrier(const struct igma_chip *, int);
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static u_int32_t igma_reg_read(const struct igma_chip *, int);
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static void igma_reg_write(const struct igma_chip *, int, u_int32_t);
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static u_int8_t igma_vga_read(const struct igma_chip *, int);
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static void igma_vga_write(const struct igma_chip *, int , u_int8_t);
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#if 0
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static u_int8_t igma_crtc_read(const struct igma_chip *, int);
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static void igma_crtc_write(const struct igma_chip *, int, u_int8_t);
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#endif
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static const struct i2c_bitbang_ops igma_i2cbb_ops = {
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igma_i2cbb_set_bits,
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igma_i2cbb_set_dir,
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igma_i2cbb_read,
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{ 1, 2, 0, 1 }
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};
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static const struct igma_chip_ops igma_bus_ops = {
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igma_reg_barrier,
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igma_reg_read,
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igma_reg_write,
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igma_vga_read,
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igma_vga_write,
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#if 0
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igma_crtc_read,
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igma_crtc_write,
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#endif
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};
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static struct igma_product {
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u_int16_t product;
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int gentype;
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int num_pipes;
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} const igma_products[] = {
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/* i830 */
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{ PCI_PRODUCT_INTEL_82830MP_IV, 200,2 },
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/* i845g */
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{ PCI_PRODUCT_INTEL_82845G_IGD, 200,2 },
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/* i85x */
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{ PCI_PRODUCT_INTEL_82855GM_IGD, 200,2 },
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// 0x358e ?
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/* i865g */
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{ PCI_PRODUCT_INTEL_82865_IGD, 200,2 },
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/* i915g */
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{ PCI_PRODUCT_INTEL_82915G_IGD, 200,2 },
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{ PCI_PRODUCT_INTEL_E7221_IGD, 200,2 },
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/* i915gm */
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{ PCI_PRODUCT_INTEL_82915GM_IGD, 300,2 },
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/* i945g */
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{ PCI_PRODUCT_INTEL_82945P_IGD, 300,2 },
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/* i945gm */
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{ PCI_PRODUCT_INTEL_82945GM_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82945GM_IGD_1, 300,2 },
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{ PCI_PRODUCT_INTEL_82945GME_IGD, 300,2 },
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/* i965g */
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{ PCI_PRODUCT_INTEL_82946GZ_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82G35_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82G35_IGD_1, 300,2 },
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{ PCI_PRODUCT_INTEL_82965Q_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82965Q_IGD_1, 300,2 },
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{ PCI_PRODUCT_INTEL_82965G_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82965G_IGD_1, 300,2 },
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/* g33 */
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{ PCI_PRODUCT_INTEL_82G33_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82G33_IGD_1, 300,2 },
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{ PCI_PRODUCT_INTEL_82Q33_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82Q33_IGD_1, 300,2 },
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{ PCI_PRODUCT_INTEL_82Q35_IGD, 300,2 },
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{ PCI_PRODUCT_INTEL_82Q35_IGD_1, 300,2 },
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/* pineview */
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{ PCI_PRODUCT_INTEL_PINEVIEW_IGD, 350,2 },
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{ PCI_PRODUCT_INTEL_PINEVIEW_M_IGD, 350,2 },
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/* i965gm */
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{ PCI_PRODUCT_INTEL_82965PM_IGD, 400,2 },
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{ PCI_PRODUCT_INTEL_82965PM_IGD_1, 400,2 },
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{ PCI_PRODUCT_INTEL_82965GME_IGD, 400,2 },
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/* gm45 */
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{ PCI_PRODUCT_INTEL_82GM45_IGD, 450,2 },
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{ PCI_PRODUCT_INTEL_82GM45_IGD_1, 450,2 },
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/* g45 */
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{ PCI_PRODUCT_INTEL_82IGD_E_IGD, 450,2 },
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{ PCI_PRODUCT_INTEL_82Q45_IGD, 450,2 },
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{ PCI_PRODUCT_INTEL_82G45_IGD, 450,2 },
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{ PCI_PRODUCT_INTEL_82G41_IGD, 450,2 },
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{ PCI_PRODUCT_INTEL_82B43_IGD, 450,2 },
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// 0x2e92 ?
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/* ironlake d */
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{ PCI_PRODUCT_INTEL_IRONLAKE_D_IGD, 500,2 },
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/* ironlake m */
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{ PCI_PRODUCT_INTEL_IRONLAKE_M_IGD, 500,2 },
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/* sandy bridge */
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD, 600,2 },
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_1, 600,2 },
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_2, 600,2 },
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/* sandy bridge m */
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD, 600,2 },
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_1, 600,2 },
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_2, 600,2 },
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/* sandy bridge s */
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{ PCI_PRODUCT_INTEL_SANDYBRIDGE_S_IGD, 600,2 },
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/* ivy bridge */
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_IGD, 700,3 },
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_IGD_1, 700,3 },
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/* ivy bridge m */
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_M_IGD, 700,3 },
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_M_IGD_1, 700,3 },
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/* ivy bridge s */
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD, 700,3 },
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{ PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD_1, 700,3 },
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#if 0
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/* valleyview d */
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/* valleyview m */
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{ PCI_PRODUCT_INTEL_HASWELL_IGD_1, 800,3 },
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/* haswell d */
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{ PCI_PRODUCT_INTEL_HASWELL_IGD, 800,3 },
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{ PCI_PRODUCT_INTEL_HASWELL_IGD_1, 800,3 },
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/* haswell m */
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/* broadwell d */
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/* broadwell m */
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#endif
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};
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static int
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igma_newpch_match(const struct pci_attach_args *pa)
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{
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
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return 0;
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switch (0xff00 & PCI_PRODUCT(pa->pa_id)) {
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case 0x3b00: /* ibex peak */
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case 0x1c00: /* cougar point */
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case 0x1e00: /* panther point */
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case 0x8c00: /* lynx point */
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case 0x9c00: /* lynx point lp */
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return 1;
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}
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return 0;
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}
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static const struct igma_product *
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igma_lookup(const struct pci_attach_args *pa)
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{
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const struct igma_product *ip;
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int i;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
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return NULL;
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for (i=0; i < __arraycount(igma_products); ++i) {
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ip = &igma_products[i];
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if (PCI_PRODUCT(pa->pa_id) == ip->product)
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return ip;
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}
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return NULL;
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}
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static void
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igma_product_to_chip(const struct pci_attach_args *pa, struct igma_chip *cd)
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{
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const struct igma_product *ip;
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struct pci_attach_args PA;
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ip = igma_lookup(pa);
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KASSERT(ip != NULL);
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cd->ops = &igma_bus_ops;
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cd->num_gmbus = 6;
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cd->num_pipes = ip->num_pipes;
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cd->quirks = 0;
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cd->backlight_factor = 1;
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cd->gpio_offset = OLD_GPIOA;
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cd->vga_cntrl = PCH_VGA_CNTRL;
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cd->backlight_cntrl = OLD_BLC_PWM_CTL;
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cd->backlight_cntrl2 = OLD_BLC_PWM_CTL2;
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PA = *pa;
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if (pci_find_device(&PA, igma_newpch_match)) {
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cd->gpio_offset = PCH_GPIOA;
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cd->vga_cntrl = CPU_VGA_CNTRL;
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cd->backlight_cntrl = CPU_BLC_PWM_CTL;
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cd->backlight_cntrl2 = CPU_BLC_PWM_CTL2;
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}
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switch (ip->gentype) {
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case 200:
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cd->backlight_factor = 2;
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break;
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case 300:
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case 350:
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cd->backlight_factor = 2;
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cd->quirks |= IGMA_PFITDISABLE_QUIRK;
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break;
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case 450:
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cd->pri_cntrl = PRI_CTRL_NOTRICKLE;
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cd->quirks |= IGMA_PLANESTART_QUIRK;
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break;
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default:
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cd->pri_cntrl = 0;
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break;
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}
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}
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static void
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igma_adjust_chip(struct igma_softc *sc, struct igma_chip *cd)
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{
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const struct igma_chip_ops *co = cd->ops;
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u_int32_t reg;
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reg = co->read_reg(cd, cd->vga_cntrl);
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if (reg & VGA_PIPE_B_SELECT)
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cd->use_pipe = 1;
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}
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static int
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igma_print(void *aux, const char *pnp)
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{
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if (pnp)
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aprint_normal("drm at %s", pnp);
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return (UNCONF);
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}
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static int
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igma_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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const struct igma_product *ip;
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if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY)
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return 0;
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ip = igma_lookup(pa);
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if (ip != NULL)
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return 100;
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return 0;
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}
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static void
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igma_attach(device_t parent, device_t self, void *aux)
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{
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struct igma_softc *sc = device_private(self);
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const struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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struct igma_attach_args iaa;
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bus_space_tag_t gttmmt, gmt, regt;
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bus_space_handle_t gttmmh, gmh, regh;
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bus_addr_t gttmmb, gmb;
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pci_aprint_devinfo(pa, NULL);
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sc->sc_dev = self;
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/* Initialize according to chip type */
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igma_product_to_chip(pa, &sc->sc_chip);
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if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM,
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BUS_SPACE_MAP_LINEAR,
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>tmmt, >tmmh, >tmmb, NULL)) {
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aprint_error_dev(sc->sc_dev, "unable to map GTTMM\n");
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return;
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}
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sc->sc_chip.mmiot = gttmmt;
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if (bus_space_subregion(gttmmt, gttmmh, 0, 2*1024*1024,
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&sc->sc_chip.mmioh)) {
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aprint_error_dev(sc->sc_dev, "unable to submap MMIO\n");
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return;
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}
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sc->sc_chip.gttt = gttmmt;
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if (bus_space_subregion(gttmmt, gttmmh, 2*1024*1024, 2*1024*1024,
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&sc->sc_chip.gtth)) {
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aprint_error_dev(sc->sc_dev, "unable to submap GTT\n");
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return;
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}
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if (pci_mapreg_map(pa, PCI_BAR2, PCI_MAPREG_TYPE_MEM,
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BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE,
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&gmt, &gmh, &gmb, NULL)) {
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aprint_error_dev(sc->sc_dev, "unable to map aperture\n");
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return;
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}
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sc->sc_chip.gmt = gmt;
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sc->sc_chip.gmh = gmh;
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sc->sc_chip.gmb = gmb;
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if (pci_mapreg_map(pa, PCI_BAR4, PCI_MAPREG_TYPE_IO, 0,
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®t, ®h, NULL, NULL)) {
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aprint_error_dev(sc->sc_dev, "unable to map IO registers\n");
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return;
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}
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#if NVGA > 0
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iaa.iaa_console = vga_cndetach() ? true : false;
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#else
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iaa.iaa_console = 0;
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#endif
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sc->sc_chip.vgat = regt;
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if (bus_space_map(regt, 0x3c0, 0x10, 0, &sc->sc_chip.vgah)) {
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aprint_error_dev(sc->sc_dev, "unable to map VGA registers\n");
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return;
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}
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/* Check hardware for more information */
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igma_adjust_chip(sc, &sc->sc_chip);
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aprint_normal("%s: VGA_CNTRL: 0x%x\n",device_xname(sc->sc_dev),
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sc->sc_chip.vga_cntrl);
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aprint_normal("%s: GPIO_OFFSET: 0x%x\n",device_xname(sc->sc_dev),
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sc->sc_chip.gpio_offset);
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aprint_normal("%s: BACKLIGHT_CTRL: 0x%x\n",device_xname(sc->sc_dev),
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sc->sc_chip.backlight_cntrl);
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aprint_normal("%s: BACKLIGHT_CTRL2: 0x%x\n",device_xname(sc->sc_dev),
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sc->sc_chip.backlight_cntrl2);
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#if NIGMAFB > 0
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strcpy(iaa.iaa_name, "igmafb");
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iaa.iaa_chip = sc->sc_chip;
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config_found_ia(sc->sc_dev, "igmabus", &iaa, igma_print);
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#endif
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igma_i2c_attach(sc);
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}
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static void
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igma_i2c_attach(struct igma_softc *sc)
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{
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struct igma_i2c *ii;
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int i;
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#if 0
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struct i2cbus_attach_args iba;
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#endif
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for (i=0; i<sc->sc_chip.num_gmbus; ++i) {
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ii = &sc->sc_ii[i];
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ii->ii_sc = sc;
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/* XXX */
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ii->ii_reg = sc->sc_chip.gpio_offset - PCH_GPIOA;
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switch (i) {
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case 0:
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ii->ii_reg += PCH_GPIOB;
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ii->ii_name = "ssc";
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break;
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case 1:
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ii->ii_reg += PCH_GPIOA;
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ii->ii_name = "vga";
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break;
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case 2:
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ii->ii_reg += PCH_GPIOC;
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ii->ii_name = "panel";
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break;
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case 3:
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ii->ii_reg += PCH_GPIOD;
|
|
ii->ii_name = "dpc";
|
|
break;
|
|
case 4:
|
|
ii->ii_reg += PCH_GPIOE;
|
|
ii->ii_name = "dpb";
|
|
break;
|
|
case 5:
|
|
ii->ii_reg += PCH_GPIOF;
|
|
ii->ii_name = "dpd";
|
|
break;
|
|
default:
|
|
panic("don't know GMBUS %d\n",i);
|
|
}
|
|
|
|
iic_tag_init(&ii->ii_i2c);
|
|
ii->ii_i2c.ic_cookie = ii;
|
|
ii->ii_i2c.ic_send_start = igma_i2c_send_start;
|
|
ii->ii_i2c.ic_send_stop = igma_i2c_send_stop;
|
|
ii->ii_i2c.ic_initiate_xfer = igma_i2c_initiate_xfer;
|
|
ii->ii_i2c.ic_read_byte = igma_i2c_read_byte;
|
|
ii->ii_i2c.ic_write_byte = igma_i2c_write_byte;
|
|
|
|
#if 0
|
|
memset(&iba, 0, sizeof(iba));
|
|
iba.iba_tag = &ii->ii_i2c;
|
|
config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/*
|
|
* I2C interface
|
|
*/
|
|
|
|
static int
|
|
igma_i2c_send_start(void *cookie, int flags)
|
|
{
|
|
return i2c_bitbang_send_start(cookie, flags, &igma_i2cbb_ops);
|
|
}
|
|
|
|
static int
|
|
igma_i2c_send_stop(void *cookie, int flags)
|
|
{
|
|
return i2c_bitbang_send_stop(cookie, flags, &igma_i2cbb_ops);
|
|
}
|
|
|
|
static int
|
|
igma_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
|
|
{
|
|
return i2c_bitbang_initiate_xfer(cookie, addr, flags, &igma_i2cbb_ops);
|
|
}
|
|
|
|
static int
|
|
igma_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
|
|
{
|
|
return i2c_bitbang_read_byte(cookie, valp, flags, &igma_i2cbb_ops);
|
|
}
|
|
|
|
static int
|
|
igma_i2c_write_byte(void *cookie, uint8_t val, int flags)
|
|
{
|
|
return i2c_bitbang_write_byte(cookie, val, flags, &igma_i2cbb_ops);
|
|
}
|
|
|
|
static void
|
|
igma_i2cbb_set_bits(void *cookie, uint32_t bits)
|
|
{
|
|
struct igma_i2c *ii = cookie;
|
|
struct igma_softc *sc = ii->ii_sc;
|
|
const struct igma_chip *cd = &sc->sc_chip;
|
|
const struct igma_chip_ops *co = cd->ops;
|
|
uint32_t reg;
|
|
|
|
reg = co->read_reg(cd, ii->ii_reg);
|
|
reg &= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE;
|
|
|
|
if ((bits | ii->ii_dir) & 1)
|
|
/* make data input, signal is pulled high */
|
|
reg |= GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
|
|
else
|
|
/* make data output, signal is driven low */
|
|
reg |= GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK
|
|
| GPIO_DATA_VAL_MASK;
|
|
|
|
if (bits & 2)
|
|
/* make clock input, signal is pulled high */
|
|
reg |= GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
|
|
else
|
|
/* make clock output, signal is driven low */
|
|
reg |= GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK
|
|
| GPIO_CLOCK_VAL_MASK;
|
|
|
|
co->write_reg(cd, ii->ii_reg, reg);
|
|
#if 1
|
|
reg = co->read_reg(cd, ii->ii_reg);
|
|
#else
|
|
co->barrier(cd, ii->ii_reg);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
igma_i2cbb_set_dir(void *cookie, uint32_t bits)
|
|
{
|
|
struct igma_i2c *ii = cookie;
|
|
|
|
ii->ii_dir = bits;
|
|
}
|
|
|
|
static uint32_t
|
|
igma_i2cbb_read(void *cookie)
|
|
{
|
|
struct igma_i2c *ii = cookie;
|
|
struct igma_softc *sc = ii->ii_sc;
|
|
const struct igma_chip *cd = &sc->sc_chip;
|
|
const struct igma_chip_ops *co = cd->ops;
|
|
uint32_t reg;
|
|
int sda, scl;
|
|
|
|
reg = co->read_reg(cd, ii->ii_reg);
|
|
|
|
sda = reg & GPIO_DATA_VAL_IN;
|
|
scl = reg & GPIO_CLOCK_VAL_IN;
|
|
|
|
reg = (sda ? 1 : 0) | (scl ? 2 : 0);
|
|
return reg;
|
|
}
|
|
|
|
static void
|
|
igma_reg_barrier(const struct igma_chip *cd, int r)
|
|
{
|
|
bus_space_barrier(cd->mmiot, cd->mmioh, r, sizeof(u_int32_t),
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
}
|
|
|
|
static u_int32_t
|
|
igma_reg_read(const struct igma_chip *cd, int r)
|
|
{
|
|
return bus_space_read_4(cd->mmiot, cd->mmioh, r);
|
|
}
|
|
|
|
static void
|
|
igma_reg_write(const struct igma_chip *cd, int r, u_int32_t v)
|
|
{
|
|
bus_space_write_4(cd->mmiot, cd->mmioh, r, v);
|
|
}
|
|
|
|
static u_int8_t
|
|
igma_vga_read(const struct igma_chip *cd, int r)
|
|
{
|
|
bus_space_write_1(cd->vgat, cd->vgah, 0x4, r | 0x20);
|
|
return bus_space_read_1(cd->vgat, cd->vgah, 0x5);
|
|
}
|
|
|
|
static void
|
|
igma_vga_write(const struct igma_chip *cd, int r, u_int8_t v)
|
|
{
|
|
bus_space_write_1(cd->vgat, cd->vgah, 0x4, r | 0x20);
|
|
bus_space_write_1(cd->vgat, cd->vgah, 0x5, v);
|
|
}
|
|
|
|
#if 0
|
|
static u_int8_t
|
|
igma_crtc_read(const struct igma_chip *cd, int r)
|
|
{
|
|
bus_space_write_1(cd->crtct, cd->crtch, 0x4, r);
|
|
return bus_space_read_1(cd->crtct, cd->crtch, 0x5);
|
|
}
|
|
|
|
static void
|
|
igma_crtc_write(const struct igma_chip *cd, int r, u_int8_t v)
|
|
{
|
|
bus_space_write_1(cd->crtct, cd->crtch, 0x4, r);
|
|
bus_space_write_1(cd->crtct, cd->crtch, 0x5, v);
|
|
}
|
|
#endif
|