535 lines
17 KiB
C
535 lines
17 KiB
C
/* $NetBSD: ahcisata_pci.c,v 1.57 2020/01/18 11:26:11 simonb Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.57 2020/01/18 11:26:11 simonb Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_ahcisata_pci.h"
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#endif
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#ifdef _KERNEL_OPT
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#include "opt_ahcisata_pci.h"
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#endif
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#include <sys/types.h>
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#include <sys/kmem.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/disklabel.h>
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#include <sys/pmf.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/ic/ahcisatavar.h>
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struct ahci_pci_quirk {
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pci_vendor_id_t vendor; /* Vendor ID */
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pci_product_id_t product; /* Product ID */
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int quirks; /* quirks; same as sc_ahci_quirks */
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};
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static const struct ahci_pci_quirk ahci_pci_quirks[] = {
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
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AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
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AHCI_PCI_QUIRK_FORCE },
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/* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
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AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
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AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
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AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
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AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
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AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
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AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
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AHCI_PCI_QUIRK_FORCE },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
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AHCI_QUIRK_BADPMP },
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{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
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AHCI_QUIRK_BADPMP },
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};
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struct ahci_pci_softc {
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struct ahci_softc ah_sc;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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pci_intr_handle_t *sc_pihp;
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int sc_nintr;
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void **sc_ih;
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};
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static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
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static int ahci_pci_match(device_t, cfdata_t, void *);
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static void ahci_pci_attach(device_t, device_t, void *);
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static int ahci_pci_detach(device_t, int);
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static void ahci_pci_childdetached(device_t, device_t);
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static bool ahci_pci_resume(device_t, const pmf_qual_t *);
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CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
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ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
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NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
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#define AHCI_PCI_ABAR_CAVIUM 0x10
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static int
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ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
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{
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int i;
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for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
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if (vendor == ahci_pci_quirks[i].vendor &&
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product == ahci_pci_quirks[i].product)
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return ahci_pci_quirks[i].quirks;
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return 0;
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}
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static int
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ahci_pci_abar(struct pci_attach_args *pa)
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{
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
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if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
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return AHCI_PCI_ABAR_CAVIUM;
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}
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}
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return AHCI_PCI_ABAR;
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}
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static int
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ahci_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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bus_space_tag_t regt;
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bus_space_handle_t regh;
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bus_size_t size;
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int ret = 0;
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bool force;
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force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
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PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
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/* if wrong class and not forced by quirks, don't match */
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if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
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((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
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PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
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PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
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(force == false))
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return 0;
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int bar = ahci_pci_abar(pa);
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pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
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if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0)
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return 0;
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if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
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PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
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(bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
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(force == true))
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ret = 3;
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bus_space_unmap(regt, regh, size);
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return ret;
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}
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static int
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ahci_pci_intr_establish(struct ahci_softc *sc, int port)
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{
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struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
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device_t self = sc->sc_atac.atac_dev;
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char intrbuf[PCI_INTRSTR_LEN];
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char intr_xname[INTRDEVNAMEBUF];
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const char *intrstr;
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int vec;
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int (*intr_handler)(void *);
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void *intr_arg;
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KASSERT(psc->sc_pihp != NULL);
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KASSERT(psc->sc_nintr > 0);
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snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
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if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
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/* Only one interrupt, established on vector 0 */
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intr_handler = ahci_intr;
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intr_arg = sc;
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vec = 0;
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if (psc->sc_ih[vec] != NULL) {
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/* Already established, nothing more to do */
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goto out;
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}
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} else {
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/*
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* Theoretically AHCI device can have less MSI/MSI-X vectors
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* than supported ports. Hardware is allowed to revert
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* to single message MSI, but not required to do so.
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* So handle the case when it did not revert to single MSI.
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* In this case last available interrupt vector is used
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* for port == max vector, and all further ports.
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* This last vector must use the general interrupt handler,
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* since it needs to be able to handle several ports.
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* NOTE: such case was never actually observed yet
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*/
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if (sc->sc_atac.atac_nchannels > psc->sc_nintr
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&& port >= (psc->sc_nintr - 1)) {
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intr_handler = ahci_intr;
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intr_arg = sc;
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vec = psc->sc_nintr - 1;
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if (psc->sc_ih[vec] != NULL) {
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/* Already established, nothing more to do */
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goto out;
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}
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if (port == vec) {
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/* Print error once */
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aprint_error_dev(self,
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"port %d independant interrupt vector not "
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"available, sharing with further ports",
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port);
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}
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} else {
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/* Vector according to port */
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KASSERT(port < psc->sc_nintr);
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KASSERT(psc->sc_ih[port] == NULL);
|
|
intr_handler = ahci_intr_port;
|
|
intr_arg = &sc->sc_channels[port];
|
|
vec = port;
|
|
|
|
snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
|
|
device_xname(self), port);
|
|
}
|
|
}
|
|
|
|
intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
|
|
sizeof(intrbuf));
|
|
psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
|
|
psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
|
|
if (psc->sc_ih == NULL) {
|
|
aprint_error_dev(self, "couldn't establish interrupt");
|
|
if (intrstr != NULL)
|
|
aprint_error(" at %s", intrstr);
|
|
aprint_error("\n");
|
|
goto fail;
|
|
}
|
|
aprint_normal_dev(self, "interrupting at %s\n", intrstr);
|
|
|
|
out:
|
|
return 0;
|
|
|
|
fail:
|
|
return EAGAIN;
|
|
}
|
|
|
|
static void
|
|
ahci_pci_attach(device_t parent, device_t self, void *aux)
|
|
{
|
|
struct pci_attach_args *pa = aux;
|
|
struct ahci_pci_softc *psc = device_private(self);
|
|
struct ahci_softc *sc = &psc->ah_sc;
|
|
bool ahci_cap_64bit;
|
|
bool ahci_bad_64bit;
|
|
pcireg_t reg;
|
|
|
|
sc->sc_atac.atac_dev = self;
|
|
|
|
int bar = ahci_pci_abar(pa);
|
|
pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
|
|
if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
|
|
NULL, &sc->sc_ahcis) != 0) {
|
|
aprint_error_dev(self, "can't map ahci registers\n");
|
|
return;
|
|
}
|
|
psc->sc_pc = pa->pa_pc;
|
|
psc->sc_pcitag = pa->pa_tag;
|
|
|
|
pci_aprint_devinfo(pa, "AHCI disk controller");
|
|
|
|
int counts[PCI_INTR_TYPE_SIZE] = {
|
|
[PCI_INTR_TYPE_INTX] = 1,
|
|
[PCI_INTR_TYPE_MSI] = 1,
|
|
[PCI_INTR_TYPE_MSIX] = -1,
|
|
};
|
|
|
|
/* Allocate and establish the interrupt. */
|
|
if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
|
|
aprint_error_dev(self, "can't allocate handler\n");
|
|
goto fail;
|
|
}
|
|
|
|
psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
|
|
psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
|
|
sc->sc_intr_establish = ahci_pci_intr_establish;
|
|
|
|
sc->sc_dmat = pa->pa_dmat;
|
|
|
|
sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
|
|
PCI_PRODUCT(pa->pa_id));
|
|
|
|
ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
|
|
ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
|
|
|
|
if (pci_dma64_available(pa) && ahci_cap_64bit) {
|
|
if (!ahci_bad_64bit)
|
|
sc->sc_dmat = pa->pa_dmat64;
|
|
aprint_verbose_dev(self, "64-bit DMA%s\n",
|
|
(sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
|
|
}
|
|
|
|
if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
|
|
AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
|
|
sc->sc_atac_capflags = ATAC_CAP_RAID;
|
|
} else {
|
|
AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
|
|
}
|
|
|
|
reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
|
|
reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
|
|
pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
|
|
|
|
ahci_attach(sc);
|
|
|
|
if (!pmf_device_register(self, NULL, ahci_pci_resume))
|
|
aprint_error_dev(self, "couldn't establish power handler\n");
|
|
|
|
return;
|
|
fail:
|
|
if (psc->sc_pihp != NULL) {
|
|
pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
|
|
psc->sc_pihp = NULL;
|
|
}
|
|
if (sc->sc_ahcis) {
|
|
bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
|
|
sc->sc_ahcis = 0;
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
static void
|
|
ahci_pci_childdetached(device_t dv, device_t child)
|
|
{
|
|
struct ahci_pci_softc *psc = device_private(dv);
|
|
struct ahci_softc *sc = &psc->ah_sc;
|
|
|
|
ahci_childdetached(sc, child);
|
|
}
|
|
|
|
static int
|
|
ahci_pci_detach(device_t dv, int flags)
|
|
{
|
|
struct ahci_pci_softc *psc;
|
|
struct ahci_softc *sc;
|
|
int rv;
|
|
|
|
psc = device_private(dv);
|
|
sc = &psc->ah_sc;
|
|
|
|
if ((rv = ahci_detach(sc, flags)))
|
|
return rv;
|
|
|
|
pmf_device_deregister(dv);
|
|
|
|
if (psc->sc_ih != NULL) {
|
|
for (int intr = 0; intr < psc->sc_nintr; intr++) {
|
|
if (psc->sc_ih[intr] != NULL) {
|
|
pci_intr_disestablish(psc->sc_pc,
|
|
psc->sc_ih[intr]);
|
|
psc->sc_ih[intr] = NULL;
|
|
}
|
|
}
|
|
|
|
kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
|
|
psc->sc_ih = NULL;
|
|
}
|
|
|
|
if (psc->sc_pihp != NULL) {
|
|
pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
|
|
psc->sc_pihp = NULL;
|
|
}
|
|
|
|
bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool
|
|
ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
|
|
{
|
|
struct ahci_pci_softc *psc = device_private(dv);
|
|
struct ahci_softc *sc = &psc->ah_sc;
|
|
int s;
|
|
|
|
s = splbio();
|
|
ahci_resume(sc);
|
|
splx(s);
|
|
|
|
return true;
|
|
}
|