380 lines
9.1 KiB
C
380 lines
9.1 KiB
C
/* $NetBSD: pic_uic.c,v 1.4 2013/11/19 12:46:43 kiyohara Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pic_uic.c,v 1.4 2013/11/19 12:46:43 kiyohara Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/evcnt.h>
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#include <sys/cpu.h>
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#include <machine/intr.h>
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#include <machine/psl.h>
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/spr.h>
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#include <powerpc/ibm4xx/cpu.h>
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#include <powerpc/pic/picvar.h>
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/*
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* Number of interrupts (hard + soft), irq number legality test,
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* mapping of irq number to mask and a way to pick irq number
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* off a mask of active intrs.
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*/
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#define IRQ_TO_MASK(irq) (0x80000000UL >> ((irq) & 0x1f))
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#define IRQ_OF_MASK(mask) __builtin_clz(mask)
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static void uic_enable_irq(struct pic_ops *, int, int);
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static void uic_disable_irq(struct pic_ops *, int);
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static int uic_get_irq(struct pic_ops *, int);
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static void uic_ack_irq(struct pic_ops *, int);
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static void uic_establish_irq(struct pic_ops *, int, int, int);
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struct uic {
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uint32_t uic_intr_enable; /* cached intr enable mask */
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uint32_t (*uic_mf_intr_status)(void);
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uint32_t (*uic_mf_intr_enable)(void);
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void (*uic_mt_intr_enable)(uint32_t);
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void (*uic_mt_intr_ack)(uint32_t);
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};
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/*
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* Platform specific code may override any of the above.
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*/
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#ifdef PPC_IBM403
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#include <powerpc/ibm4xx/dcr403cgx.h>
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static uint32_t
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uic403_mfdcr_intr_status(void)
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{
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return mfdcr(DCR_EXISR);
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}
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static uint32_t
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uic403_mfdcr_intr_enable(void)
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{
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return mfdcr(DCR_EXIER);
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}
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static void
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uic403_mtdcr_intr_ack(uint32_t v)
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{
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mtdcr(DCR_EXISR, v);
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}
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static void
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uic403_mtdcr_intr_enable(uint32_t v)
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{
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mtdcr(DCR_EXIER, v);
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}
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struct uic uic403 = {
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.uic_intr_enable = 0,
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.uic_mf_intr_status = uic403_mfdcr_intr_status,
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.uic_mf_intr_enable = uic403_mfdcr_intr_enable,
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.uic_mt_intr_enable = uic403_mtdcr_intr_enable,
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.uic_mt_intr_ack = uic403_mtdcr_intr_ack,
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};
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struct pic_ops pic_uic403 = {
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.pic_cookie = &uic403,
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.pic_numintrs = 32,
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.pic_enable_irq = uic_enable_irq,
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.pic_reenable_irq = uic_enable_irq,
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.pic_disable_irq = uic_disable_irq,
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.pic_establish_irq = uic_establish_irq,
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.pic_get_irq = uic_get_irq,
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.pic_ack_irq = uic_ack_irq,
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.pic_finish_setup = NULL,
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.pic_name = "uic0"
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};
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#else /* Generic 405/440/460 Universal Interrupt Controller */
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#include <powerpc/ibm4xx/dcr4xx.h>
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#include "opt_uic.h"
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/* 405EP/405GP/405GPr/Virtex-4 */
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static uint32_t
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uic0_mfdcr_intr_status(void)
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{
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return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR);
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}
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static uint32_t
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uic0_mfdcr_intr_enable(void)
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{
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return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER);
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}
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static void
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uic0_mtdcr_intr_ack(uint32_t v)
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{
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mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v);
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}
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static void
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uic0_mtdcr_intr_enable(uint32_t v)
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{
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mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v);
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}
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struct uic uic0 = {
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.uic_intr_enable = 0,
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.uic_mf_intr_status = uic0_mfdcr_intr_status,
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.uic_mf_intr_enable = uic0_mfdcr_intr_enable,
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.uic_mt_intr_enable = uic0_mtdcr_intr_enable,
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.uic_mt_intr_ack = uic0_mtdcr_intr_ack,
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};
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struct pic_ops pic_uic0 = {
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.pic_cookie = &uic0,
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.pic_numintrs = 32,
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.pic_enable_irq = uic_enable_irq,
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.pic_reenable_irq = uic_enable_irq,
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.pic_disable_irq = uic_disable_irq,
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.pic_establish_irq = uic_establish_irq,
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.pic_get_irq = uic_get_irq,
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.pic_ack_irq = uic_ack_irq,
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.pic_finish_setup = NULL,
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.pic_name = "uic0"
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};
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#ifdef MULTIUIC
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/* 440EP/440GP/440SP/405EX/440SPe/440GX */
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static uint32_t
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uic1_mfdcr_intr_status(void)
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{
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return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR);
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}
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static uint32_t
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uic1_mfdcr_intr_enable(void)
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{
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return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER);
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}
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static void
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uic1_mtdcr_intr_ack(uint32_t v)
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{
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mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v);
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}
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static void
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uic1_mtdcr_intr_enable(uint32_t v)
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{
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mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v);
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}
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extern struct pic_ops pic_uic1;
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static void
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uic1_finish_setup(struct pic_ops *pic)
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{
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intr_establish(30, IST_LEVEL, IPL_HIGH, pic_handle_intr, &pic_uic1);
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}
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struct uic uic1 = {
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.uic_intr_enable = 0,
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.uic_mf_intr_status = uic1_mfdcr_intr_status,
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.uic_mf_intr_enable = uic1_mfdcr_intr_enable,
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.uic_mt_intr_enable = uic1_mtdcr_intr_enable,
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.uic_mt_intr_ack = uic1_mtdcr_intr_ack,
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};
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struct pic_ops pic_uic1 = {
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.pic_cookie = &uic1,
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.pic_numintrs = 32,
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.pic_enable_irq = uic_enable_irq,
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.pic_reenable_irq = uic_enable_irq,
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.pic_disable_irq = uic_disable_irq,
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.pic_establish_irq = uic_establish_irq,
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.pic_get_irq = uic_get_irq,
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.pic_ack_irq = uic_ack_irq,
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.pic_finish_setup = uic1_finish_setup,
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.pic_name = "uic1"
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};
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/* 440EP/440GP/440SP/405EX/440SPe */
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static uint32_t
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uic2_mfdcr_intr_status(void)
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{
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return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR);
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}
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static uint32_t
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uic2_mfdcr_intr_enable(void)
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{
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return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER);
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}
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static void
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uic2_mtdcr_intr_ack(uint32_t v)
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{
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mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v);
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}
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static void
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uic2_mtdcr_intr_enable(uint32_t v)
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{
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mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v);
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}
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extern struct pic_ops pic_uic2;
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static void
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uic2_finish_setup(struct pic_ops *pic)
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{
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intr_establish(28, IST_LEVEL, IPL_HIGH, pic_handle_intr, &pic_uic2);
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}
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static struct uic uic2 = {
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.uic_intr_enable = 0,
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.uic_mf_intr_status = uic2_mfdcr_intr_status,
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.uic_mf_intr_enable = uic2_mfdcr_intr_enable,
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.uic_mt_intr_enable = uic2_mtdcr_intr_enable,
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.uic_mt_intr_ack = uic2_mtdcr_intr_ack,
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};
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struct pic_ops pic_uic2 = {
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.pic_cookie = &uic2,
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.pic_numintrs = 32,
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.pic_enable_irq = uic_enable_irq,
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.pic_reenable_irq = uic_enable_irq,
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.pic_disable_irq = uic_disable_irq,
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.pic_establish_irq = uic_establish_irq,
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.pic_get_irq = uic_get_irq,
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.pic_ack_irq = uic_ack_irq,
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.pic_finish_setup = uic2_finish_setup,
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.pic_name = "uic2"
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};
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#endif /* MULTIUIC */
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#endif /* !PPC_IBM403 */
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/* Write External Enable Immediate */
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#define wrteei(en) __asm volatile ("wrteei %0" : : "K"(en))
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/* Enforce In Order Execution of I/O */
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#define eieio() __asm volatile ("eieio")
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/*
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* Set up interrupt mapping array.
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*/
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void
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intr_init(void)
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{
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#ifdef PPC_IBM403
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struct pic_ops * const pic = &pic_uic403;
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#else
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struct pic_ops * const pic = &pic_uic0;
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#endif
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struct uic * const uic = pic->pic_cookie;
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uic->uic_mt_intr_enable(0x00000000); /* mask all */
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uic->uic_mt_intr_ack(0xffffffff); /* acknowledge all */
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pic_add(pic);
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}
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static void
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uic_disable_irq(struct pic_ops *pic, int irq)
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{
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struct uic * const uic = pic->pic_cookie;
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const uint32_t irqmask = IRQ_TO_MASK(irq);
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if ((uic->uic_intr_enable & irqmask) == 0)
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return;
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uic->uic_intr_enable ^= irqmask;
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(*uic->uic_mt_intr_enable)(uic->uic_intr_enable);
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#ifdef IRQ_DEBUG
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printf("%s: %s: irq=%d, mask=%08x\n", __func__,
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pic->pic_name, irq, irqmask);
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#endif
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}
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static void
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uic_enable_irq(struct pic_ops *pic, int irq, int type)
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{
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struct uic * const uic = pic->pic_cookie;
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const uint32_t irqmask = IRQ_TO_MASK(irq);
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if ((uic->uic_intr_enable & irqmask) != 0)
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return;
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uic->uic_intr_enable ^= irqmask;
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(*uic->uic_mt_intr_enable)(uic->uic_intr_enable);
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#ifdef IRQ_DEBUG
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printf("%s: %s: irq=%d, mask=%08x\n", __func__,
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pic->pic_name, irq, irqmask);
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#endif
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}
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static void
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uic_ack_irq(struct pic_ops *pic, int irq)
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{
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struct uic * const uic = pic->pic_cookie;
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const uint32_t irqmask = IRQ_TO_MASK(irq);
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(*uic->uic_mt_intr_ack)(irqmask);
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}
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static int
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uic_get_irq(struct pic_ops *pic, int dummy)
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{
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struct uic * const uic = pic->pic_cookie;
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const uint32_t irqmask = (*uic->uic_mf_intr_status)();
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if (irqmask == 0)
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return 255;
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return IRQ_OF_MASK(irqmask);
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}
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/*
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* Register an interrupt handler.
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*/
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static void
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uic_establish_irq(struct pic_ops *pic, int irq, int type, int ipl)
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{
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}
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