797 lines
22 KiB
C
797 lines
22 KiB
C
/* $NetBSD: npx.c,v 1.2 2004/04/06 16:23:33 cl Exp $ */
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/* NetBSD: npx.c,v 1.103 2004/03/21 10:56:24 simonb Exp */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)npx.c 7.2 (Berkeley) 5/12/91
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*/
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/*-
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* Copyright (c) 1994, 1995, 1998 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1990 William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)npx.c 7.2 (Berkeley) 5/12/91
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.2 2004/04/06 16:23:33 cl Exp $");
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#if 0
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#define IPRINTF(x) printf x
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#else
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#define IPRINTF(x)
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#endif
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#include "opt_cputype.h"
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#include "opt_multiprocessor.h"
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#include "opt_xen.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/vmmeter.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/cpufunc.h>
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#include <machine/pcb.h>
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#include <machine/trap.h>
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#include <machine/specialreg.h>
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#include <machine/pio.h>
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#include <machine/i8259.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <i386/isa/npxvar.h>
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#ifdef XEN
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#include <machine/xen.h>
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#include <machine/hypervisor.h>
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#endif
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/*
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* 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
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*
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* We do lazy initialization and switching using the TS bit in cr0 and the
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* MDL_USEDFPU bit in mdproc.
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*
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* DNA exceptions are handled like this:
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*
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* 1) If there is no NPX, return and go to the emulator.
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* 2) If someone else has used the NPX, save its state into that process's PCB.
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* 3a) If MDL_USEDFPU is not set, set it and initialize the NPX.
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* 3b) Otherwise, reload the process's previous NPX state.
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*
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* When a process is created or exec()s, its saved cr0 image has the TS bit
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* set and the MDL_USEDFPU bit clear. The MDL_USEDFPU bit is set when the
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* process first gets a DNA and the NPX is initialized. The TS bit is turned
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* off when the NPX is used, and turned on again later when the process's NPX
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* state is saved.
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*/
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#define fldcw(addr) __asm("fldcw %0" : : "m" (*addr))
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#define fnclex() __asm("fnclex")
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#define fninit() __asm("fninit")
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#define fnsave(addr) __asm("fnsave %0" : "=m" (*addr))
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#define fnstcw(addr) __asm("fnstcw %0" : "=m" (*addr))
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#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*addr))
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#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fwait")
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#define frstor(addr) __asm("frstor %0" : : "m" (*addr))
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#define fwait() __asm("fwait")
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#ifndef XEN
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#define clts() __asm("clts")
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#define stts() lcr0(rcr0() | CR0_TS)
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#else
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#define clts()
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#define stts() HYPERVISOR_fpu_taskswitch()
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#endif
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int npxdna(struct cpu_info *);
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static int npxdna_notset(struct cpu_info *);
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static int npxdna_s87(struct cpu_info *);
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#ifdef I686_CPU
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static int npxdna_xmm(struct cpu_info *);
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#endif /* I686_CPU */
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static int x86fpflags_to_ksiginfo(u_int32_t flags);
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#ifdef I686_CPU
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#define fxsave(addr) __asm("fxsave %0" : "=m" (*addr))
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#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*addr))
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#endif /* I686_CPU */
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static enum npx_type npx_type;
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volatile u_int npx_intrs_while_probing;
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volatile u_int npx_traps_while_probing;
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extern int i386_fpu_present;
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extern int i386_fpu_exception;
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extern int i386_fpu_fdivbug;
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struct npx_softc *npx_softc;
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static __inline void
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fpu_save(union savefpu *addr)
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{
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#ifdef I686_CPU
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if (i386_use_fxsave)
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{
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fxsave(&addr->sv_xmm);
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/* FXSAVE doesn't FNINIT like FNSAVE does -- so do it here. */
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fninit();
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} else
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#endif /* I686_CPU */
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fnsave(&addr->sv_87);
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}
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static int
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npxdna_notset(struct cpu_info *ci)
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{
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panic("npxdna vector not initialized");
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}
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int (*npxdna_func)(struct cpu_info *) = npxdna_notset;
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#if 0
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static int
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npxdna_empty(struct cpu_info *ci)
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{
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/* raise a DNA TRAP, math_emulate would take over eventually */
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IPRINTF(("Emul"));
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return 0;
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}
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/*
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* This calls i8259_* directly, but currently we can count on systems
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* having a i8259 compatible setup all the time. Maybe have to change
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* that in the future.
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*/
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enum npx_type
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npxprobe1(bus_space_tag_t iot, bus_space_handle_t ioh, int irq)
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{
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struct gate_descriptor save_idt_npxintr;
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struct gate_descriptor save_idt_npxtrap;
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enum npx_type rv = NPX_NONE;
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u_long save_eflags;
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int control;
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int status;
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unsigned irqmask;
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save_eflags = read_eflags();
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disable_intr();
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save_idt_npxintr = idt[NRSVIDT + irq];
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save_idt_npxtrap = idt[16];
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setgate(&idt[NRSVIDT + irq], probeintr, 0, SDT_SYS386IGT, SEL_KPL,
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GSEL(GCODE_SEL, SEL_KPL));
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setgate(&idt[16], probetrap, 0, SDT_SYS386TGT, SEL_KPL,
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GSEL(GCODE_SEL, SEL_KPL));
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irqmask = i8259_setmask(~((1 << IRQ_SLAVE) | (1 << irq)));
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/*
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* Partially reset the coprocessor, if any. Some BIOS's don't reset
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* it after a warm boot.
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*/
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/* full reset on some systems, NOP on others */
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bus_space_write_1(iot, ioh, 1, 0);
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delay(1000);
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/* clear BUSY# latch */
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bus_space_write_1(iot, ioh, 0, 0);
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/*
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* We set CR0 in locore to trap all ESC and WAIT instructions.
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* We have to turn off the CR0_EM bit temporarily while probing.
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*/
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lcr0(rcr0() & ~(CR0_EM|CR0_TS));
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enable_intr();
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/*
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* Finish resetting the coprocessor, if any. If there is an error
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* pending, then we may get a bogus IRQ13, but probeintr() will handle
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* it OK. Bogus halts have never been observed, but we enabled
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* IRQ13 and cleared the BUSY# latch early to handle them anyway.
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*/
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fninit();
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delay(1000); /* wait for any IRQ13 (fwait might hang) */
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/*
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* Check for a status of mostly zero.
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*/
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status = 0x5a5a;
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fnstsw(&status);
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if ((status & 0xb8ff) == 0) {
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/*
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* Good, now check for a proper control word.
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*/
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control = 0x5a5a;
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fnstcw(&control);
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if ((control & 0x1f3f) == 0x033f) {
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/*
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* We have an npx, now divide by 0 to see if exception
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* 16 works.
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*/
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control &= ~(1 << 2); /* enable divide by 0 trap */
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fldcw(&control);
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npx_traps_while_probing = npx_intrs_while_probing = 0;
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fp_divide_by_0();
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if (npx_traps_while_probing != 0) {
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/*
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* Good, exception 16 works.
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*/
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rv = NPX_EXCEPTION;
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i386_fpu_exception = 1;
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} else if (npx_intrs_while_probing != 0) {
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/*
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* Bad, we are stuck with IRQ13.
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*/
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rv = NPX_INTERRUPT;
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} else {
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/*
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* Worse, even IRQ13 is broken. Use emulator.
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*/
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rv = NPX_BROKEN;
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}
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}
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}
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disable_intr();
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lcr0(rcr0() | (CR0_EM|CR0_TS));
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irqmask = i8259_setmask(irqmask);
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idt[NRSVIDT + irq] = save_idt_npxintr;
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idt_allocmap[NRSVIDT + irq] = 1;
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idt[16] = save_idt_npxtrap;
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write_eflags(save_eflags);
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if ((rv == NPX_NONE) || (rv == NPX_BROKEN)) {
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/* No FPU. Handle it here, npxattach won't be called */
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npxdna_func = npxdna_empty;
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}
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return (rv);
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}
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#endif
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void npxinit(ci)
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struct cpu_info *ci;
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{
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lcr0(rcr0() & ~(CR0_EM|CR0_TS));
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fninit();
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if (npx586bug1(4195835, 3145727) != 0) {
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i386_fpu_fdivbug = 1;
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printf("%s: WARNING: Pentium FDIV bug detected!\n",
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ci->ci_dev->dv_xname);
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}
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lcr0(rcr0() | (CR0_TS));
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}
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/*
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* Common attach routine.
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*/
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void
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npxattach(struct npx_softc *sc)
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{
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npx_softc = sc;
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npx_type = sc->sc_type;
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i386_fpu_present = 1;
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#ifdef I686_CPU
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if (i386_use_fxsave)
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npxdna_func = npxdna_xmm;
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else
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#endif /* I686_CPU */
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npxdna_func = npxdna_s87;
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}
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/*
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* Record the FPU state and reinitialize it all except for the control word.
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* Then generate a SIGFPE.
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*
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* Reinitializing the state allows naive SIGFPE handlers to longjmp without
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* doing any fixups.
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*
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* XXX there is currently no way to pass the full error state to signal
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* handlers, and if this is a nested interrupt there is no way to pass even
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* a status code! So there is no way to have a non-naive SIGFPE handler. At
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* best a handler could do an fninit followed by an fldcw of a static value.
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* fnclex would be of little use because it would leave junk on the FPU stack.
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* Returning from the handler would be even less safe than usual because
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* IRQ13 exception handling makes exceptions even less precise than usual.
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*/
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int
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npxintr(void *arg, struct intrframe iframe)
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{
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struct cpu_info *ci = curcpu();
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struct lwp *l = ci->ci_fpcurlwp;
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union savefpu *addr;
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struct intrframe *frame = &iframe;
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struct npx_softc *sc;
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ksiginfo_t ksi;
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sc = npx_softc;
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uvmexp.traps++;
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IPRINTF(("%s: fp intr\n", ci->ci_dev->dv_xname));
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panic("not supported\n");
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/*
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* Clear the interrupt latch.
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*/
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, 0);
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/*
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* If we're saving, ignore the interrupt. The FPU will generate
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* another one when we restore the state later.
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*/
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if (ci->ci_fpsaving)
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return (1);
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if (l == NULL || npx_type == NPX_NONE) {
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printf("npxintr: l = %p, curproc = %p, npx_type = %d\n",
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l, curproc, npx_type);
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printf("npxintr: came from nowhere");
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return 1;
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}
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#ifdef DIAGNOSTIC
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/*
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* At this point, fpcurlwp should be curlwp. If it wasn't, the TS
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* bit should be set, and we should have gotten a DNA exception.
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*/
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if (l != curlwp)
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panic("npxintr: wrong process");
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#endif
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/*
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* Find the address of fpcurproc's saved FPU state. (Given the
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* invariant above, this is always the one in curpcb.)
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*/
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addr = &l->l_addr->u_pcb.pcb_savefpu;
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/*
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* Save state. This does an implied fninit. It had better not halt
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* the CPU or we'll hang.
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*/
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fpu_save(addr);
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fwait();
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if (i386_use_fxsave) {
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fldcw(&addr->sv_xmm.sv_env.en_cw);
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/*
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* FNINIT doesn't affect MXCSR or the XMM registers;
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* no need to re-load MXCSR here.
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*/
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} else
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fldcw(&addr->sv_87.sv_env.en_cw);
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fwait();
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/*
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* Remember the exception status word and tag word. The current
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* (almost fninit'ed) fpu state is in the fpu and the exception
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* state just saved will soon be junk. However, the implied fninit
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* doesn't change the error pointers or register contents, and we
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* preserved the control word and will copy the status and tag
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* words, so the complete exception state can be recovered.
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*/
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if (i386_use_fxsave) {
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addr->sv_xmm.sv_ex_sw = addr->sv_xmm.sv_env.en_sw;
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addr->sv_xmm.sv_ex_tw = addr->sv_xmm.sv_env.en_tw;
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} else {
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addr->sv_87.sv_ex_sw = addr->sv_87.sv_env.en_sw;
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addr->sv_87.sv_ex_tw = addr->sv_87.sv_env.en_tw;
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}
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/*
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* Pass exception to process.
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*/
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if (USERMODE(frame->if_cs, frame->if_eflags)) {
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/*
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* Interrupt is essentially a trap, so we can afford to call
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* the SIGFPE handler (if any) as soon as the interrupt
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* returns.
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*
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* XXX little or nothing is gained from this, and plenty is
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* lost - the interrupt frame has to contain the trap frame
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* (this is otherwise only necessary for the rescheduling trap
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* in doreti, and the frame for that could easily be set up
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* just before it is used).
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*/
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l->l_md.md_regs = (struct trapframe *)&frame->if_gs;
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KSI_INIT_TRAP(&ksi);
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ksi.ksi_signo = SIGFPE;
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ksi.ksi_addr = (void *)frame->if_eip;
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/*
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* Encode the appropriate code for detailed information on
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* this exception.
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*/
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if (i386_use_fxsave) {
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ksi.ksi_code =
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x86fpflags_to_ksiginfo(addr->sv_xmm.sv_ex_sw);
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ksi.ksi_trap = (int)addr->sv_xmm.sv_ex_sw;
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} else {
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ksi.ksi_code =
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x86fpflags_to_ksiginfo(addr->sv_87.sv_ex_sw);
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ksi.ksi_trap = (int)addr->sv_87.sv_ex_sw;
|
|
}
|
|
|
|
trapsignal(l, &ksi);
|
|
} else {
|
|
/*
|
|
* This is a nested interrupt. This should only happen when
|
|
* an IRQ13 occurs at the same time as a higher-priority
|
|
* interrupt.
|
|
*
|
|
* XXX
|
|
* Currently, we treat this like an asynchronous interrupt, but
|
|
* this has disadvantages.
|
|
*/
|
|
psignal(l->l_proc, SIGFPE);
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
|
|
/* map x86 fp flags to ksiginfo fp codes */
|
|
/* see table 8-4 of the IA-32 Intel Architecture */
|
|
/* Software Developer's Manual, Volume 1 */
|
|
/* XXX punting on the stack fault with FLTINV */
|
|
static int
|
|
x86fpflags_to_ksiginfo(u_int32_t flags)
|
|
{
|
|
int i;
|
|
static int x86fp_ksiginfo_table[] = {
|
|
FPE_FLTINV, /* bit 0 - invalid operation */
|
|
FPE_FLTRES, /* bit 1 - denormal operand */
|
|
FPE_FLTDIV, /* bit 2 - divide by zero */
|
|
FPE_FLTOVF, /* bit 3 - fp overflow */
|
|
FPE_FLTUND, /* bit 4 - fp underflow */
|
|
FPE_FLTRES, /* bit 5 - fp precision */
|
|
FPE_FLTINV, /* bit 6 - stack fault */
|
|
};
|
|
|
|
for(i=0;i < sizeof(x86fp_ksiginfo_table)/sizeof(int); i++) {
|
|
if (flags & (1 << i))
|
|
return(x86fp_ksiginfo_table[i]);
|
|
}
|
|
/* punt if flags not set */
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Implement device not available (DNA) exception
|
|
*
|
|
* Save the previous state, if necessary, and restore our last
|
|
* saved state.
|
|
* XXX If we were the last process to use the FPU, we should be able
|
|
* to simply return.
|
|
*/
|
|
|
|
#ifdef I686_CPU
|
|
static int
|
|
npxdna_xmm(struct cpu_info *ci)
|
|
{
|
|
struct lwp *l;
|
|
int s;
|
|
#ifdef XXXXENDEBUG_LOW
|
|
struct trapframe *f = (struct trapframe *)((uint32_t *)(void *)&ci)[1];
|
|
#endif
|
|
|
|
KDASSERT(i386_use_fxsave == 1);
|
|
|
|
if (ci->ci_fpsaving) {
|
|
printf("recursive npx trap; cr0=%x\n", rcr0());
|
|
return (0);
|
|
}
|
|
|
|
s = splipi(); /* lock out IPI's while we clean house.. */
|
|
#ifdef MULTIPROCESSOR
|
|
l = ci->ci_curlwp;
|
|
#else
|
|
l = curlwp;
|
|
#endif
|
|
IPRINTF(("%s: dna for lwp %p at %p, eax %p\n", ci->ci_dev->dv_xname,
|
|
l, (void *)f->tf_eip, (void *)f->tf_eax));
|
|
/*
|
|
* XXX should have a fast-path here when no save/restore is necessary
|
|
*/
|
|
/*
|
|
* Initialize the FPU state to clear any exceptions. If someone else
|
|
* was using the FPU, save their state (which does an implicit
|
|
* initialization).
|
|
*/
|
|
if (ci->ci_fpcurlwp != NULL) {
|
|
IPRINTF(("Save"));
|
|
npxsave_cpu(ci, 1);
|
|
} else {
|
|
IPRINTF(("Init"));
|
|
fninit();
|
|
fwait();
|
|
}
|
|
splx(s);
|
|
|
|
IPRINTF(("%s: done saving\n", ci->ci_dev->dv_xname));
|
|
KDASSERT(ci->ci_fpcurlwp == NULL);
|
|
#ifndef MULTIPROCESSOR
|
|
KDASSERT(l->l_addr->u_pcb.pcb_fpcpu == NULL);
|
|
#else
|
|
if (l->l_addr->u_pcb.pcb_fpcpu != NULL)
|
|
npxsave_lwp(l, 1);
|
|
#endif
|
|
l->l_addr->u_pcb.pcb_cr0 &= ~CR0_TS;
|
|
clts();
|
|
s = splipi();
|
|
ci->ci_fpcurlwp = l;
|
|
l->l_addr->u_pcb.pcb_fpcpu = ci;
|
|
splx(s);
|
|
|
|
if ((l->l_md.md_flags & MDL_USEDFPU) == 0) {
|
|
fldcw(&l->l_addr->u_pcb.pcb_savefpu.sv_xmm.sv_env.en_cw);
|
|
l->l_md.md_flags |= MDL_USEDFPU;
|
|
} else {
|
|
fxrstor(&l->l_addr->u_pcb.pcb_savefpu.sv_xmm);
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
#endif /* I686_CPU */
|
|
|
|
static int
|
|
npxdna_s87(struct cpu_info *ci)
|
|
{
|
|
struct lwp *l;
|
|
int s;
|
|
|
|
KDASSERT(i386_use_fxsave == 0);
|
|
|
|
if (ci->ci_fpsaving) {
|
|
printf("recursive npx trap; cr0=%x\n", rcr0());
|
|
return (0);
|
|
}
|
|
|
|
s = splipi(); /* lock out IPI's while we clean house.. */
|
|
#ifdef MULTIPROCESSOR
|
|
l = ci->ci_curlwp;
|
|
#else
|
|
l = curlwp;
|
|
#endif
|
|
|
|
IPRINTF(("%s: dna for lwp %p\n", ci->ci_dev->dv_xname, l));
|
|
/*
|
|
* If someone else was using our FPU, save their state (which does an
|
|
* implicit initialization); otherwise, initialize the FPU state to
|
|
* clear any exceptions.
|
|
*/
|
|
if (ci->ci_fpcurlwp != NULL)
|
|
npxsave_cpu(ci, 1);
|
|
else {
|
|
clts();
|
|
IPRINTF(("%s: fp init\n", ci->ci_dev->dv_xname));
|
|
fninit();
|
|
fwait();
|
|
stts();
|
|
}
|
|
splx(s);
|
|
|
|
IPRINTF(("%s: done saving\n", ci->ci_dev->dv_xname));
|
|
KDASSERT(ci->ci_fpcurlwp == NULL);
|
|
#ifndef MULTIPROCESSOR
|
|
KDASSERT(l->l_addr->u_pcb.pcb_fpcpu == NULL);
|
|
#else
|
|
if (l->l_addr->u_pcb.pcb_fpcpu != NULL)
|
|
npxsave_lwp(l, 1);
|
|
#endif
|
|
l->l_addr->u_pcb.pcb_cr0 &= ~CR0_TS;
|
|
clts();
|
|
s = splipi();
|
|
ci->ci_fpcurlwp = l;
|
|
l->l_addr->u_pcb.pcb_fpcpu = ci;
|
|
splx(s);
|
|
|
|
|
|
if ((l->l_md.md_flags & MDL_USEDFPU) == 0) {
|
|
fldcw(&l->l_addr->u_pcb.pcb_savefpu.sv_87.sv_env.en_cw);
|
|
l->l_md.md_flags |= MDL_USEDFPU;
|
|
} else {
|
|
/*
|
|
* The following frstor may cause an IRQ13 when the state being
|
|
* restored has a pending error. The error will appear to have
|
|
* been triggered by the current (npx) user instruction even
|
|
* when that instruction is a no-wait instruction that should
|
|
* not trigger an error (e.g., fnclex). On at least one 486
|
|
* system all of the no-wait instructions are broken the same
|
|
* as frstor, so our treatment does not amplify the breakage.
|
|
* On at least one 386/Cyrix 387 system, fnclex works correctly
|
|
* while frstor and fnsave are broken, so our treatment breaks
|
|
* fnclex if it is the first FPU instruction after a context
|
|
* switch.
|
|
*/
|
|
frstor(&l->l_addr->u_pcb.pcb_savefpu.sv_87);
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
npxsave_cpu (struct cpu_info *ci, int save)
|
|
{
|
|
struct lwp *l;
|
|
int s;
|
|
|
|
KDASSERT(ci == curcpu());
|
|
|
|
l = ci->ci_fpcurlwp;
|
|
if (l == NULL)
|
|
return;
|
|
|
|
IPRINTF(("%s: fp CPU %s lwp %p\n", ci->ci_dev->dv_xname,
|
|
save? "save" : "flush", l));
|
|
|
|
if (save) {
|
|
#ifdef DIAGNOSTIC
|
|
if (ci->ci_fpsaving != 0)
|
|
panic("npxsave_cpu: recursive save!");
|
|
#endif
|
|
/*
|
|
* Set ci->ci_fpsaving, so that any pending exception will be
|
|
* thrown away. (It will be caught again if/when the FPU
|
|
* state is restored.)
|
|
*
|
|
* XXX on i386 and earlier, this routine should always be
|
|
* called at spl0; if it might called with the NPX interrupt
|
|
* masked, it would be necessary to forcibly unmask the NPX
|
|
* interrupt so that it could succeed.
|
|
* XXX this is irrelevant on 486 and above (systems
|
|
* which report FP failures via traps rather than irq13).
|
|
* XXX punting for now..
|
|
*/
|
|
clts();
|
|
ci->ci_fpsaving = 1;
|
|
fpu_save(&l->l_addr->u_pcb.pcb_savefpu);
|
|
ci->ci_fpsaving = 0;
|
|
}
|
|
|
|
/*
|
|
* We set the TS bit in the saved CR0 for this process, so that it
|
|
* will get a DNA exception on any FPU instruction and force a reload.
|
|
*/
|
|
l->l_addr->u_pcb.pcb_cr0 |= CR0_TS;
|
|
|
|
s = splipi();
|
|
l->l_addr->u_pcb.pcb_fpcpu = NULL;
|
|
ci->ci_fpcurlwp = NULL;
|
|
splx(s);
|
|
}
|
|
|
|
/*
|
|
* Save l's FPU state, which may be on this processor or another processor.
|
|
*
|
|
* The FNSAVE instruction clears the FPU state. Rather than reloading the FPU
|
|
* immediately, we clear fpcurproc and turn on CR0_TS to force a DNA and a
|
|
* reload of the FPU state the next time we try to use it. This routine
|
|
* is only called when forking, core dumping, or debugging, or swapping,
|
|
* so the lazy reload at worst forces us to trap once per fork(), and at best
|
|
* saves us a reload once per fork().
|
|
*/
|
|
void
|
|
npxsave_lwp(struct lwp *l, int save)
|
|
{
|
|
struct cpu_info *ci = curcpu();
|
|
struct cpu_info *oci;
|
|
|
|
KDASSERT(l->l_addr != NULL);
|
|
|
|
oci = l->l_addr->u_pcb.pcb_fpcpu;
|
|
if (oci == NULL)
|
|
return;
|
|
|
|
IPRINTF(("%s: fp %s lwp %p\n", ci->ci_dev->dv_xname,
|
|
save? "save" : "flush", l));
|
|
|
|
#if defined(MULTIPROCESSOR)
|
|
if (oci == ci) {
|
|
int s = splipi();
|
|
npxsave_cpu(ci, save);
|
|
splx(s);
|
|
} else {
|
|
#ifdef DIAGNOSTIC
|
|
int spincount;
|
|
#endif
|
|
|
|
IPRINTF(("%s: fp ipi to %s %s lwp %p\n",
|
|
ci->ci_dev->dv_xname,
|
|
oci->ci_dev->dv_xname,
|
|
save? "save" : "flush", l));
|
|
|
|
x86_send_ipi(oci,
|
|
save ? X86_IPI_SYNCH_FPU : X86_IPI_FLUSH_FPU);
|
|
|
|
#ifdef DIAGNOSTIC
|
|
spincount = 0;
|
|
#endif
|
|
while (l->l_addr->u_pcb.pcb_fpcpu != NULL)
|
|
#ifdef DIAGNOSTIC
|
|
{
|
|
spincount++;
|
|
if (spincount > 10000000) {
|
|
panic("fp_save ipi didn't");
|
|
}
|
|
}
|
|
#else
|
|
__insn_barrier();
|
|
;
|
|
#endif
|
|
}
|
|
#else
|
|
KASSERT(ci->ci_fpcurlwp == l);
|
|
npxsave_cpu(ci, save);
|
|
#endif
|
|
}
|