fe3273fbb4
This adds support for EtherExpress/16 cards with 16k of RAM, and in the process adds general support for PIO mode on these cards. This entails changing the way the i82586 driver handles bus barriers, since it doesn't allow for strange cases like this. This has been tested on the i386 port with the 'ix' driver in both 16KB (which was the source of the problem) and 32KB modes, as well as with the 'ef' driver. I've tested it (briefly) with 'ei' on arm26 as well. In theory, drivers other than 'ix' should follow precisely the same code paths as before.
342 lines
9.0 KiB
C
342 lines
9.0 KiB
C
/* $NetBSD: if_ie.c,v 1.9 2001/01/22 22:28:44 bjh21 Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#include <uvm/uvm_extern.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <dev/ic/i82586reg.h>
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#include <dev/ic/i82586var.h>
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#include <mvme68k/dev/if_iereg.h>
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#include <mvme68k/dev/pcctwovar.h>
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#include <mvme68k/dev/pcctworeg.h>
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int ie_pcctwo_match __P((struct device *, struct cfdata *, void *));
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void ie_pcctwo_attach __P((struct device *, struct device *, void *));
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struct ie_pcctwo_softc {
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struct ie_softc ps_ie;
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bus_space_tag_t ps_bust;
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bus_space_handle_t ps_bush;
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};
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struct cfattach ie_pcctwo_ca = {
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sizeof(struct ie_pcctwo_softc), ie_pcctwo_match, ie_pcctwo_attach
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};
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extern struct cfdriver ie_cd;
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/* Functions required by the i82586 MI driver */
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static void ie_reset __P((struct ie_softc *, int));
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static int ie_intrhook __P((struct ie_softc *, int));
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static void ie_hwinit __P((struct ie_softc *));
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static void ie_atten __P((struct ie_softc *));
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static void ie_copyin __P((struct ie_softc *, void *, int, size_t));
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static void ie_copyout __P((struct ie_softc *, const void *, int, size_t));
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static u_int16_t ie_read_16 __P((struct ie_softc *, int));
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static void ie_write_16 __P((struct ie_softc *, int, u_int16_t));
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static void ie_write_24 __P((struct ie_softc *, int, int));
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/*
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* i82596 Support Routines for MVME1[67][27] Boards
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*/
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static void
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ie_reset(sc, why)
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struct ie_softc *sc;
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int why;
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{
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struct ie_pcctwo_softc *ps;
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u_int32_t scp_addr;
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ps = (struct ie_pcctwo_softc *) sc;
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switch (why) {
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case CHIP_PROBE:
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case CARD_RESET:
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bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_UPPER,
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IE_MPU_RESET);
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bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_LOWER, 0);
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delay(1000);
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/*
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* Set the BUSY and BUS_USE bytes here, since the MI code
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* incorrectly assumes it can use byte addressing to set it.
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* (due to wrong-endianess of the chip)
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*/
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ie_write_16(sc, IE_ISCP_BUSY(sc->iscp), 1);
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ie_write_16(sc, IE_SCP_BUS_USE(sc->scp), 0x50);
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scp_addr = sc->scp + (u_int) sc->sc_iobase;
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scp_addr |= IE_MPU_SCP_ADDRESS;
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bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_UPPER,
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scp_addr & 0xffff);
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bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_LOWER,
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(scp_addr >> 16) & 0xffff);
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delay(1000);
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break;
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}
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}
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/* ARGSUSED */
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static int
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ie_intrhook(sc, when)
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struct ie_softc *sc;
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int when;
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{
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u_int8_t reg;
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if (when == INTR_EXIT) {
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reg = pcc2_reg_read(sys_pcctwo, PCC2REG_ETH_ICSR);
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reg |= PCCTWO_ICR_ICLR;
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pcc2_reg_write(sys_pcctwo, PCC2REG_ETH_ICSR, reg);
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}
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return (0);
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}
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/* ARGSUSED */
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static void
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ie_hwinit(sc)
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struct ie_softc *sc;
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{
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u_int8_t reg;
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reg = pcc2_reg_read(sys_pcctwo, PCC2REG_ETH_ICSR);
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reg |= PCCTWO_ICR_IEN | PCCTWO_ICR_ICLR;
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pcc2_reg_write(sys_pcctwo, PCC2REG_ETH_ICSR, reg);
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}
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static void
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ie_atten(sc)
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struct ie_softc *sc;
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{
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struct ie_pcctwo_softc *ps;
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ps = (struct ie_pcctwo_softc *) sc;
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bus_space_write_4(ps->ps_bust, ps->ps_bush, IE_MPUREG_CA, 0);
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}
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static void
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ie_copyin(sc, dst, offset, size)
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struct ie_softc *sc;
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void *dst;
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int offset;
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size_t size;
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{
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if (size == 0) /* This *can* happen! */
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return;
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#if 0
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bus_space_read_region_1(sc->bt, sc->bh, offset, dst, size);
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#else
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/* A minor optimisation ;-) */
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bcopy((void *) ((u_long) sc->bh + (u_long) offset), dst, size);
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#endif
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}
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static void
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ie_copyout(sc, src, offset, size)
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struct ie_softc *sc;
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const void *src;
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int offset;
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size_t size;
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{
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if (size == 0) /* This *can* happen! */
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return;
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#if 0
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bus_space_write_region_1(sc->bt, sc->bh, offset, src, size);
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#else
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/* A minor optimisation ;-) */
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bcopy(src, (void *) ((u_long) sc->bh + (u_long) offset), size);
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#endif
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}
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static u_int16_t
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ie_read_16(sc, offset)
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struct ie_softc *sc;
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int offset;
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{
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return (bus_space_read_2(sc->bt, sc->bh, offset));
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}
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static void
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ie_write_16(sc, offset, value)
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struct ie_softc *sc;
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int offset;
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u_int16_t value;
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{
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bus_space_write_2(sc->bt, sc->bh, offset, value);
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}
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static void
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ie_write_24(sc, offset, addr)
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struct ie_softc *sc;
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int offset;
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int addr;
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{
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addr += (int) sc->sc_iobase;
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bus_space_write_2(sc->bt, sc->bh, offset, addr & 0xffff);
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bus_space_write_2(sc->bt, sc->bh, offset + 2, (addr >> 16) & 0x00ff);
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}
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/* ARGSUSED */
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int
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ie_pcctwo_match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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struct pcctwo_attach_args *pa;
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pa = args;
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if (strcmp(pa->pa_name, ie_cd.cd_name))
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return (0);
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pa->pa_ipl = cf->pcctwocf_ipl;
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return (1);
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}
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/* ARGSUSED */
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void
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ie_pcctwo_attach(parent, self, args)
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struct device *parent;
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struct device *self;
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void *args;
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{
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struct pcctwo_attach_args *pa;
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struct ie_pcctwo_softc *ps;
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struct ie_softc *sc;
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bus_dma_segment_t seg;
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int rseg;
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pa = (struct pcctwo_attach_args *) args;
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ps = (struct ie_pcctwo_softc *) self;
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sc = (struct ie_softc *) self;
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/* Map the MPU controller registers in PCCTWO space */
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ps->ps_bust = pa->pa_bust;
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bus_space_map(pa->pa_bust, pa->pa_offset, IE_MPUREG_SIZE,
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0, &ps->ps_bush);
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/* Get contiguous DMA-able memory for the IE chip */
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if (bus_dmamem_alloc(pa->pa_dmat, ether_data_buff_size, NBPG, 0,
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&seg, 1, &rseg,
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BUS_DMA_NOWAIT | BUS_DMA_ONBOARD_RAM | BUS_DMA_24BIT) != 0) {
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printf("%s: Failed to allocate ether buffer\n", self->dv_xname);
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return;
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}
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if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, ether_data_buff_size,
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(caddr_t *) & sc->sc_maddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
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printf("%s: Failed to map ether buffer\n", self->dv_xname);
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bus_dmamem_free(pa->pa_dmat, &seg, rseg);
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return;
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}
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sc->bt = pa->pa_bust;
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sc->bh = (bus_space_handle_t) sc->sc_maddr; /* XXXSCW Better way? */
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sc->sc_iobase = (void *) seg.ds_addr;
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sc->sc_msize = ether_data_buff_size;
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memset(sc->sc_maddr, 0, ether_data_buff_size);
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sc->hwreset = ie_reset;
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sc->hwinit = ie_hwinit;
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sc->chan_attn = ie_atten;
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sc->intrhook = ie_intrhook;
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sc->memcopyin = ie_copyin;
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sc->memcopyout = ie_copyout;
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sc->ie_bus_barrier = NULL;
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sc->ie_bus_read16 = ie_read_16;
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sc->ie_bus_write16 = ie_write_16;
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sc->ie_bus_write24 = ie_write_24;
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sc->sc_mediachange = NULL;
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sc->sc_mediastatus = NULL;
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sc->scp = 0;
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sc->iscp = sc->scp + ((IE_SCP_SZ + 15) & ~15);
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sc->scb = sc->iscp + IE_ISCP_SZ;
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sc->buf_area = sc->scb + IE_SCB_SZ;
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sc->buf_area_sz = sc->sc_msize - (sc->buf_area - sc->scp);
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/*
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* BUS_USE -> Interrupt Active High (edge-triggered),
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* Lock function enabled,
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* Internal bus throttle timer triggering,
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* 82586 operating mode.
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*/
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ie_write_16(sc, IE_SCP_BUS_USE(sc->scp), 0x50);
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ie_write_24(sc, IE_SCP_ISCP(sc->scp), sc->iscp);
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ie_write_16(sc, IE_ISCP_SCB(sc->iscp), sc->scb);
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ie_write_24(sc, IE_ISCP_BASE(sc->iscp), sc->scp);
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/* This has the side-effect of resetting the chip */
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i82586_proberam(sc);
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/* Attach the MI back-end */
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i82586_attach(sc, "onboard", mvme_ea, NULL, 0, 0);
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/* Finally, hook the hardware interrupt */
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pcctwointr_establish(PCCTWOV_LANC_IRQ, i82586_intr, pa->pa_ipl, sc);
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}
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