85 lines
3.1 KiB
C
85 lines
3.1 KiB
C
/* $NetBSD: pxa2x0var.h,v 1.2 2003/06/05 13:48:28 scw Exp $ */
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/*
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* Copyright (c) 2002 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Genetec Corporation.
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* 4. The name of Genetec Corporation may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_XSCALE_PXA2X0VAR_H_
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#define _ARM_XSCALE_PXA2X0VAR_H_
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#include <arm/sa11x0/sa11x0_var.h>
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/* PXA2X0's integrated peripheral bus. */
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typedef int (* pxa2x0_irq_handler_t)(void *);
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struct pxaip_attach_args {
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struct sa11x0_attach_args pxa_sa;
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bus_dma_tag_t pxa_dmat;
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int pxa_index; /* to specify device by index number */
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#define pxa_iot pxa_sa.sa_iot
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#define pxa_addr pxa_sa.sa_addr
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#define pxa_size pxa_sa.sa_size
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#define pxa_intr pxa_sa.sa_intr
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};
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extern struct bus_space pxa2x0_bs_tag;
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extern struct arm32_bus_dma_tag pxa2x0_bus_dma_tag;
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extern struct bus_space pxa2x0_a4x_bs_tag;
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/* misc. */
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extern void pxa2x0_fcs_init(void);
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extern void pxa2x0_freq_change(int);
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extern void pxa2x0_turbo_mode(int);
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extern int pxa2x0_i2c_master_tx( int, uint8_t *, int );
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/*
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* Probe the memory controller to deterimine which SDRAM are
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* populated, and what size of SDRAM is present in each bank.
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*
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* This routine should be called from a port's initarm()
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* function, with the first parameter set to the address
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* of the memory controller's registers.
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*/
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extern void pxa2x0_probe_sdram(vaddr_t, paddr_t *, psize_t *);
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/*
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* Configure one or more clock enables in the Clock Manager's
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* CKEN register.
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*/
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extern void pxa2x0_clkman_config(u_int, boolean_t);
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#endif /* _ARM_XSCALE_PXA2X0VAR_H_ */
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