068a6eb9af
But support only PIO-mode now. Also AES-CBC not supported. Don't know how to process to AES CBC in PIO-mode. I haven't found IV registers.
126 lines
5.5 KiB
C
126 lines
5.5 KiB
C
/* $NetBSD: mvcesareg.h,v 1.1 2012/07/27 03:00:01 kiyohara Exp $ */
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/*
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* Copyright (c) 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVCESAREG_H_
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#define _MVCESAREG_H_
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#define MVCESA_SIZE 0x10000
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/*
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* Cryptographic Engine and Security Accelerator Registers
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*/
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/* DES Engine Registers */
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#define MVCESA_DESE_DOL 0xdd78 /* Data Out Low */
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#define MVCESA_DESE_DOH 0xdd7c /* Data Out High */
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#define MVCESA_DESE_DBL 0xdd70 /* Data Buffer Low */
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#define MVCESA_DESE_DBH 0xdd74 /* Data Buffer High */
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#define MVCESA_DESE_IVL 0xdd40 /* Initial Value Low */
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#define MVCESA_DESE_IVH 0xdd44 /* Initial Value High */
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#define MVCESA_DESE_K0L 0xdd48 /* Key0 Low */
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#define MVCESA_DESE_K0H 0xdd4c /* Key0 High */
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#define MVCESA_DESE_K1L 0xdd50 /* Key1 Low */
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#define MVCESA_DESE_K1H 0xdd54 /* Key1 High */
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#define MVCESA_DESE_K2L 0xdd60 /* Key2 Low */
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#define MVCESA_DESE_K2H 0xdd64 /* Key2 High */
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#define MVCESA_DESE_C 0xdd58 /* Command */
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#define MVCESA_DESE_C_DIRECTION_ENC (0 << 0)
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#define MVCESA_DESE_C_DIRECTION_DEC (1 << 0)
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#define MVCESA_DESE_C_ALGORITHM_DES (0 << 1)
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#define MVCESA_DESE_C_ALGORITHM_3DES (1 << 1)
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#define MVCESA_DESE_C_3DESMODE_EEE (0 << 2)
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#define MVCESA_DESE_C_3DESMODE_EDE (1 << 2)
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#define MVCESA_DESE_C_DESMODE_ECB (0 << 3)
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#define MVCESA_DESE_C_DESMODE_CBC (1 << 3)
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#define MVCESA_DESE_C_DATABYTESWAP (1 << 4)
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#define MVCESA_DESE_C_IVBYTESWAP (1 << 6)
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#define MVCESA_DESE_C_OUTBYTESWAP (1 << 8)
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#define MVCESA_DESE_C_READALLOW (1 << 29)
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#define MVCESA_DESE_C_ALLTERMINATION (1 << 30)
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#define MVCESA_DESE_C_TERMINATION (1 << 31)
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/* SHA-1 and MD5 Interface Registers */
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#define MVCESA_SHA1MD5I_DI 0xdd38 /* Data In */
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#define MVCESA_SHA1MD5I_BCL 0xdd20 /* Bit Count Low */
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#define MVCESA_SHA1MD5I_BCH 0xdd24 /* Bit Count High */
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#define MVCESA_SHA1MD5I_IVDA 0xdd00 /* Initial Value/Digest A */
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#define MVCESA_SHA1MD5I_IVDB 0xdd04 /* Initial Value/Digest B */
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#define MVCESA_SHA1MD5I_IVDC 0xdd08 /* Initial Value/Digest C */
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#define MVCESA_SHA1MD5I_IVDD 0xdd0c /* Initial Value/Digest D */
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#define MVCESA_SHA1MD5I_IVDE 0xdd10 /* Initial Value/Digest E */
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#define MVCESA_SHA1MD5I_AC 0xdd18 /* Authentication Command */
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#define MVCESA_SHA1MD5I_AC_ALGORITHM_MD5 (0 << 0)
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#define MVCESA_SHA1MD5I_AC_ALGORITHM_SHA1 (1 << 0)
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#define MVCESA_SHA1MD5I_AC_MODE_USEIV (0 << 1)
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#define MVCESA_SHA1MD5I_AC_MODE_CONTINUE (1 << 1)
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#define MVCESA_SHA1MD5I_AC_DATABYTESWAP (1 << 2)
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#define MVCESA_SHA1MD5I_AC_IVBYTESWAP (1 << 4)
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#define MVCESA_SHA1MD5I_AC_TERMINATION (1 << 31)
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/* AES Encryption/Decription Interface Registers */
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#define MVCESA_AES_ENCRYPTION 0xdd80
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#define MVCESA_AES_DECRYPTION 0xddc0
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#define MVCESA_AES_DIOC_OFF 0x20 /* Data In/Out Column */
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#define MVCESA_AES_DIOC_MAX 3
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#define MVCESA_AES_KC_OFF 0x00 /* Key Column */
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#define MVCESA_AES_KC_MAX 7
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#define MVCESA_AES_C 0x30 /* Command */
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#define MVCESA_AES_C_AESKEYMODE_128 (0 << 0)
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#define MVCESA_AES_C_AESKEYMODE_192 (1 << 0)
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#define MVCESA_AES_C_AESKEYMODE_256 (2 << 0)
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#define MVCESA_AES_C_AESDECMAKEKEY (1 << 2)
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#define MVCESA_AES_C_DATABYTESWAP (1 << 4)
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#define MVCESA_AES_C_OUTBYTESWAP (1 << 8)
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#define MVCESA_AES_C_TERMINATION (1 << 31)
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#define MVCESA_AES_DIOC(c) \
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(MVCESA_AES_DIOC_OFF + ((c) - MVCESA_AES_DIOC_MAX) * 4)
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#define MVCESA_AES_KC(c) \
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(MVCESA_AES_KC_OFF + ((c) - MVCESA_AES_KC_MAX) * 4)
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/* Security Accelerator Registers */
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#define MVCESA_SA_C 0xde00 /* Command */
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#define MVCESA_SA_DPS0 0xde04 /* Descriptor Pointer Session 0 */
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#define MVCESA_SA_DPS1 0xde14 /* Descriptor Pointer Session 1 */
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#define MVCESA_SA_CFG 0xde08 /* Configuration */
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#define MVCESA_SA_S 0xde0c /* Status */
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/* Interrupt Cause Registers */
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#define MVCESA_IC 0xde20 /* Interrupt Cause */
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#define MVCESA_IM 0xde24 /* Interrupt Mask */
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#define MVCESA_I_ZINT0 (1 << 0) /* auth termination */
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#define MVCESA_I_ZINT1 (1 << 1) /* DES */
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#define MVCESA_I_ZINT2 (1 << 2) /* AES encryption */
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#define MVCESA_I_ZINT3 (1 << 3) /* AES decryption */
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#define MVCESA_I_ZINT4 (1 << 4) /* enc termination */
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#define MVCESA_I_ACCINT0 (1 << 5) /* Security accelerator 0 */
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#define MVCESA_I_ACCINT1 (1 << 6) /* Security accelerator 1 */
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#define MVCESA_I_ACCANDIDMAINT0 (1 << 7) /* Acceleration and IDMA 0 */
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#define MVCESA_I_ACCANDIDMAINT1 (1 << 8) /* Acceleration and IDMA 1 */
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#endif /* _MVCESAREG_H_ */
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