1884f05354
Remove the entire idea of fasttrap interrupts since V9 traps are really cheap, the CPUs are really fast, and the completely different trap frames would make these handlers really difficult to implement. pmap_changeprot() was only used by the clock and one other place; deprecate it. probeget() and probeset() now take 64-bit addresses even in 32-bit mode so we can probe IO locations by physical addresses. Some pmap cleanup. Some more copyright cleanup.
193 lines
9.0 KiB
C
193 lines
9.0 KiB
C
/* $NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp $ */
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/*
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* Copyright (c) 1996-1999 Eduardo Horvath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Sbus device addresses are obtained from the FORTH PROMs. They come
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* in `absolute' and `relative' address flavors, so we have to handle both.
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* Relative addresses do *not* include the slot number.
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*/
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#define SBUS_BASE 0xf8000000
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#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off))
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#define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE)
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#define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25)
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#define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff)
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/*
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* Sun4u S-bus definitions. Here's where we deal w/the machine
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* dependencies of sysio.
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*
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* SYSIO implements or is the interface to several things:
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*
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* o The SBUS interface itself
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* o The IOMMU
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* o The DVMA units
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* o The interrupt controller
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* o The counter/timers
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*
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* Since it has registers to control lots of different things
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* as well as several on-board SBUS devices and external SBUS
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* slots scattered throughout its address space, it's a pain.
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*
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* One good point, however, is that all registers are 64-bit.
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*/
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struct sysioreg {
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struct upareg {
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u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
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u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
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} sys_upa;
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u_int64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */
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u_int64_t pad0;
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u_int64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
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u_int64_t reserved; /* 1fe.0000.0028 */
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u_int64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
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u_int64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
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u_int64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
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u_int64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
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u_int64_t pad1[22];
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struct perfmon {
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u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */
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u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */
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} sys_pm;
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u_int64_t pad2[990];
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struct sbusreg {
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u_int64_t sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */
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u_int64_t reserved; /* 1fe.0000.2008 */
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u_int64_t sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */
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u_int64_t sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */
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u_int64_t sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */
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u_int64_t sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */
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u_int64_t sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */
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u_int64_t sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */
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u_int64_t sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */
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u_int64_t sbus_config14; /* Slot 14 config register <macio> */ /* 1fe.0000.2048 */
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u_int64_t sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */
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} sys_sbus;
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u_int64_t pad3[117];
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struct iommureg sys_iommu; /* 1fe.0000.2400,2410 */
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u_int64_t pad4[125];
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struct iommu_strbuf sys_strbuf; /* 1fe.0000.2800-2810 */
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u_int64_t pad5[125];
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u_int64_t sbus_slot0_int; /* SBUS slot 0 interrupt map reg */ /* 1fe.0000.2c00 */
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u_int64_t sbus_slot1_int; /* SBUS slot 1 interrupt map reg */ /* 1fe.0000.2c08 */
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u_int64_t sbus_slot2_int; /* SBUS slot 2 interrupt map reg */ /* 1fe.0000.2c10 */
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u_int64_t sbus_slot3_int; /* SBUS slot 3 interrupt map reg */ /* 1fe.0000.2c18 */
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u_int64_t intr_retry; /* interrupt retry timer reg */ /* 1fe.0000.2c20 */
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u_int64_t pad6[123];
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u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */
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u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */
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u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */
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u_int64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */
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u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */
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u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */
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u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */
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u_int64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */
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u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */
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u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */
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u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */
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u_int64_t pad7;
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u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */
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u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */
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u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */
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u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */
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u_int64_t sbus_async_int_map; /* SBUS error interrupt map reg */ /* 1fe.0000.3080 */
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u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */
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u_int64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */
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u_int64_t reserved_int_map; /* reserved interrupt map reg */ /* 1fe.0000.3098 */
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u_int64_t pad8[108];
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/* Note: clear interrupt 0 registers are not really used */
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u_int64_t sbus0_clr_int[8]; /* SBUS slot 0 clear int regs 0..7 */ /* 1fe.0000.3400-3438 */
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u_int64_t sbus1_clr_int[8]; /* SBUS slot 1 clear int regs 0..7 */ /* 1fe.0000.3440-3478 */
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u_int64_t sbus2_clr_int[8]; /* SBUS slot 2 clear int regs 0..7 */ /* 1fe.0000.3480-34b8 */
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u_int64_t sbus3_clr_int[8]; /* SBUS slot 3 clear int regs 0..7 */ /* 1fe.0000.34c0-34f8 */
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u_int64_t pad9[96];
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u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.3800 */
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u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.3808 */
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u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.3810 */
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u_int64_t audio_clr_int; /* audio clear int reg */ /* 1fe.0000.3818 */
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u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.3820 */
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u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.3828 */
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u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.3830 */
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u_int64_t therm_clr_int; /* thermal warn clear int reg */ /* 1fe.0000.3838 */
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u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.3840 */
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u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.3848 */
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u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.3850 */
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u_int64_t pad10;
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u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.3860 */
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u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.3868 */
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u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.3870 */
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u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.3878 */
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u_int64_t sbus_clr_async_int; /* SBUS error clr interrupt reg */ /* 1fe.0000.3880 */
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u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.3888 */
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u_int64_t pad11[110];
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struct timer_counter {
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u_int64_t tc_count; /* timer/counter 0/1 count register */ /* ife.0000.3c00,3c10 */
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u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* ife.0000.3c08,3c18 */
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} tc[2];
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u_int64_t pad12[252];
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u_int64_t sys_svadiag; /* SBUS virtual addr diag reg */ /* 1fe.0000.4400 */
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u_int64_t pad13[31];
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u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */
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u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */
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u_int64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */
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u_int64_t pad14[32];
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u_int64_t sbus_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.4800 */
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u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.4808 */
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u_int64_t pad15[254];
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u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */
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u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */
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u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */
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u_int64_t pad16[16];
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u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */
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};
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