4285910912
Modify current_spl_level to reflect the temporary change in interrupt priority level which dispatching. Don't increment the interrupt stats for every handler in the interrupt chain. Cleaned up a number of comments. Define soft interrupt names. A few miscellaneous tidy ups.
690 lines
18 KiB
ArmAsm
690 lines
18 KiB
ArmAsm
/* $NetBSD: ofw_irq.S,v 1.7 1998/09/05 04:05:31 mark Exp $ */
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Low level irq and fiq handlers
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*
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* Created : 27/09/94
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*/
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#include "opt_irqstats.h"
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#include "opt_uvm.h"
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#include "assym.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/irqhandler.h>
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.text
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.align 0
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/*
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*
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* irq_entry
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*
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* Main entry point for the IRQ vector
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*
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* This function is called only on timer ticks, passed on to the
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* kernel from the OFW tick handler.
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*
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* For now, I am trying to re-use as much of the code from the
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* IOMD interrupt-handler as possible. In time, I will strip this
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* down to something OFW-specific.
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*
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* Here's the original, IOMD-specific description:
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* This function reads the irq request bits in the IOMD registers
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* IRQRQA, IRQRQB and DMARQ
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* It then calls an installed handler for each bit that is set.
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* The function stray_irqhandler is called if a handler is not defined
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* for a particular interrupt.
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* If a interrupt handler is found then it is called with r0 containing
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* the argument defined in the handler structure. If the field ih_arg
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* is zero then a pointer to the IRQ frame on the stack is passed instead.
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*/
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Ldisabled_mask:
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.word _disabled_mask
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Lcurrent_spl_level:
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.word _current_spl_level
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Lcurrent_intr_depth:
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.word _current_intr_depth
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Lspl_masks:
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.word _spl_masks
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Lofw_ticktmp:
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.word _ofw_ticktmp
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Lirq_entry:
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.word irq_entry
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Lofwirqstk: /* hack */
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.word ofwirqstk + 4096
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/*
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* Regsister usage
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*
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* r6 - Address of current handler
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* r7 - Pointer to handler pointer list
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of IOMD
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*/
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ASENTRY_NP(irq_entry)
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/*
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* We come here following an OFW-handled timer tick.
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*
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* We are in the SVC frame, and interrupts are disabled.
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* The state of the interrupted context is partially in
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* the registers and partially in the global storage area
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* labeled ofw_ticktmp. ofw_ticktmp is filled-in by the
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* tick callback that is invoked by OFW on the way out of
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* its interrupt handler. ofw_ticktmp contains the following:
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*
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* pc // interrupted instruction
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* lr_usr
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* sp_usr
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* r1 // makes r1 available for scratch
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* r0 // makes r0 available for scratch
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* spsr_svc // cpsr of interrupted context
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*
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* The prologue of this routine must re-construct the
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* machine state that existed at the time OFW's interrupt-
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* handler fielded the interrupt. That allows us to use
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* the rest of the code in this routine, and have it all
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* "just work."
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*/
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/*
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* Switch to IRQ mode.
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* First check the spsr in ofw_ticktmp to see what the FIQ bit should be.
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*
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* I need 2 scratch registers to do this.
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* Fortunately, r0 and r1 are already saved in ofw_ticktmp.
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* How convenient.
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*/
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ldr r0, Lofw_ticktmp
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ldr r0, [r0]
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and r0, r0, #F32_bit
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mov r1, #(I32_bit | PSR_IRQ32_MODE)
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orr r1, r1, r0
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msr cpsr_all, r1
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/* Now we're in IRQ mode. */
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/* Restore contents of ofw_ticktmp. */
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add r0, pc, #(Lofwirqstk - . - 8) /* Bummer! Mitch hasn't left me a stack. */
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ldr sp, [r0] /* I'll use my own for now... */
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ldr r0, Lofw_ticktmp /* r0 now points to ofw_ticktmp[0] */
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ldr r1, [r0], #(4*3) /* skip over saved {r0, r1} */
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msr spsr_all, r1 /* restore spsr */
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ldmia r0, {sp, lr}^ /* restore user sp and lr */
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add r0, r0, #(4*2) /* previous instruction can't writeback */
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/* this one can't use banked registers */
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ldr lr, [r0], #(-4*4) /* restore pc; point r0 at ofw_ticktmp[1] */
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add lr, lr, #4 /* pc += 4; will be decremented below */
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ldmia r0, {r0, r1} /* restore r0 and r1 */
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/* OK, the machine state should be identical now to that when */
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/* OFW fielded the interrupt. So just fall through... */
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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/*
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* Can't field this interrupt now if priority is _SPL_CLOCK
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* or higher. For now, we'll just ignore the interrupt.
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* Soon, we will have to schedule it for later action.
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*/
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ldr r0, Lcurrent_spl_level
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ldr r0, [r0]
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cmp r0, #_SPL_CLOCK
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blt ofwtakeint
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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/*
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* Stuff a bit-mask into r8 indicating which interrupts
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* are pending. In our case, that is just the timer0
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* interrupt: (1 << TIMER0). The existing code will take
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* care of invoking that handler and the softint/ast stuff
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* which follows it.
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*/
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ofwtakeint:
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mov r8, #0x00000001 /* timer interrupt pending! */
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mov r8, r8, lsl #IRQ_TIMER0
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/*
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* Note that we have entered the IRQ handler.
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* We are in SVC mode so we cannot use the processor mode
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* to determine if we are in an IRQ. Instead we will count the
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* each time the interrupt handler is nested.
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*/
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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/* Block the current requested interrupts */
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ldr r1, Ldisabled_mask
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ldr r0, [r1]
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stmfd sp!, {r0}
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orr r0, r0, r8
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/*
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* Need to block all interrupts at the IPL or lower for
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* all asserted interrupts.
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* This basically emulates hardware interrupt priority levels.
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* Means we need to go through the interrupt mask and for
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* every asserted interrupt we need to mask out all other
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* interrupts at the same or lower IPL.
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* If only we could wait until the main loop but we need to sort
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* this out first so interrupts can be re-enabled.
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*
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* This would benefit from a special ffs type routine
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*/
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mov r9, #(_SPL_LEVELS - 1)
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ldr r7, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r7, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r7, r9, lsl #2]
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mvn r2, r2
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orr r0, r0, r2
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str r0, [r1]
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ldr r0, Lcurrent_spl_level
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ldr r1, [r0]
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str r9, [r0]
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stmfd sp!, {r1}
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/* Update the irq masks */
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bl _irq_setmasks
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mrs r0, cpsr_all /* Enable IRQ's */
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r7, [pc, #irqhandlers - . - 8]
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mov r9, #0x00000001
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irqloop:
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/* This would benefit from a special ffs type routine */
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tst r8, r9 /* Is a bit set ? */
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beq nextirq /* No ? try next bit */
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ldr r6, [r7] /* Get address of first handler structure */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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beq _stray_irqhandler /* call special handler */
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ldr r0, Lcnt
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ldr r1, [r0, #(V_INTR)]
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add r1, r1, #0x00000001
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str r1, [r0, #(V_INTR)]
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/*
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* XXX: Should stats be accumlated for every interrupt routine called
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* or for every physical interrupt that is serviced.
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*/
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#ifdef IRQSTATS
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ldr r0, Lintrcnt
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ldr r1, [r6, #(IH_NUM)]
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add r0, r0, r1, lsl #2
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ldr r1, [r0]
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add r1, r1, #0x00000001
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str r1, [r0]
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#endif /* IRQSTATS */
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irqchainloop:
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add lr, pc, #nextinchain - . - 8 /* return address */
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ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */
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teq r0, #0x00000000 /* If arg is zero pass stack frame */
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addeq r0, sp, #8 /* ... stack frame */
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ldr pc, [r6, #(IH_FUNC)] /* Call handler */
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nextinchain:
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teq r0, #0x00000001 /* Was the irq serviced ? */
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beq irqdone
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ldr r6, [r6, #(IH_NEXT)]
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teq r6, #0x00000000
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bne irqchainloop
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irqdone:
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nextirq:
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add r7, r7, #0x00000004 /* update pointer to handlers */
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mov r9, r9, lsl #1 /* move on to next bit */
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teq r9, #(1 << 24) /* done the last bit ? */
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bne irqloop /* no - loop back. */
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ldmfd sp!, {r2}
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ldr r1, Lcurrent_spl_level
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str r2, [r1]
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/* Restore previous disabled mask */
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ldmfd sp!, {r2}
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ldr r1, Ldisabled_mask
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str r2, [r1]
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bl _irq_setmasks
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bl _dosoftints /* Handle the soft interrupts */
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/* Manage AST's. Maybe this should be done as a soft interrupt ? */
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ldr r0, [sp] /* Get the SPSR from stack */
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
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teq r0, #(PSR_USR32_MODE)
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ldreq r0, Lastpending /* Do we have an AST pending ? */
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ldreq r1, [r0]
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teqeq r1, #0x00000001
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beq irqast /* call the AST handler */
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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sub r1, r1, #1
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str r1, [r0]
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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/*
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* Ok, snag with current intr depth ...
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* If ast() calls mi_sleep() the current_intr_depth will not be
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* decremented until the process is woken up. This can result
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* in the system believing it is still in the interrupt handler.
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* If we are calling ast() then correct the current_intr_depth
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* before the call.
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*/
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irqast:
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mov r1, #0x00000000 /* Clear ast_pending */
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str r1, [r0]
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/* Kill IRQ's so we atomically decrement current_intr_depth */
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mrs r2, cpsr_all
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orr r3, r2, #(I32_bit)
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msr cpsr_all, r3
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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sub r1, r1, #1
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str r1, [r0]
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/* Restore IRQ's */
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msr cpsr_all, r2
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mov r0, sp
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bl _ast
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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Lspl_mask:
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.word _spl_mask /* irq's allowed at current spl level */
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Lcurrent_mask:
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.word _current_mask /* irq's that are usable */
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ENTRY(irq_setmasks)
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/* Do nothing */
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mov pc, lr
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Lcnt:
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#if defined(UVM)
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.word _uvmexp
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#else
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.word _cnt
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#endif
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Lintrcnt:
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.word _intrcnt
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irqhandlers:
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.word _irqhandlers /* Pointer to array of irqhandlers */
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Lastpending:
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.word _astpending
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.text
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.global _dotickgrovelling
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/*
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* Do magic to cause OFW to call our irq_entry
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* routine when it returns from its tick-handling.
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*
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* This consists of two sub-tasks:
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* - save some machine state in ofw_ticktmp
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* - punch some new machine state into the
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* OFW-supplied frame
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*
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* We are running in the IRQ frame, with
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* interrupts disabled.
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*
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* r0 - base of saved OFW interrupt frame, which
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* has the following format:
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*
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* pc // interrupted instruction
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* lr // lr of interrupted context
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* sp // sp of interrupted context
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* r12
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* ... // non-banked register values
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* ... // of interrupted context
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* r0
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* spsr // psr of interrupted context
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*
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*/
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_dotickgrovelling:
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/*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/
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stmfd sp!, {r1-r5} /* scratch registers r1-r5 */
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/*
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* Sub-task 1:
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*
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* Our irq_entry routine needs to re-construct
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* the state of the machine at the time OFW
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* fielded the interrupt, so that we can use
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* the rest of the standard interrupt-handling
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* code. Specifically, irq_entry needs to get
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* at the following machine state:
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*
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* pc // interrupted instruction
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* lr_usr
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* sp_usr
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* r0-r12 // the non-banked registers
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* // at the time of interruption
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* spsr // cpsr of interrupted context
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*
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* The non-banked registers will be valid at the
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* time irq_entry is called, but the other values
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* will not be. We must save them here, in the
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* ofw_ticktmp storage block. We also save r0
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* and r1 so that we have some free registers
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* when it's time to do the re-construction.
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*
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* Note that interrupts are not enabled before
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* irq_entry is entered, so we don't have to
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* worry about ofw_ticktmp getting clobbered.
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*/
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ldr r1, Lofw_ticktmp /* r1 points to ofw_ticktmp[0] */
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ldr r2, [r0, #0] /* ofwframe[0] is spsr */
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stmia r1!, {r2} /* put it in ofw_ticktmp[0] */
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ldr r2, [r0, #(4*1)] /* ofwframe[1] is saved r0 */
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stmia r1!, {r2} /* put it in ofw_ticktmp[1] */
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ldr r2, [r0, #(4*2)] /* ofwframe[2] is saved r1 */
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stmia r1!, {r2} /* put it in ofw_ticktmp[2] */
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stmia r1, {sp, lr}^ /* put {sp,lr}_usr in ofw_ticktmp[3,4]; */
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/* the user registers are still valid */
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/* because we haven't left IRQ mode */
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add r1, r1, #(4*2) /* previous instruction can't writeback */
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/* this one can't use banked registers */
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ldr r2, [r0, #(4*16)] /* ofwframe[16] is pc */
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stmia r1!, {r2} /* put it in ofw_ticktmp[5] */
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/*
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* Sub-task 2:
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*
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* Diddle the OFW-supplied frame such that
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* control passes to irq_entry when OFW does
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* its return from interrupt. There are 4
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* fields in that frame that we need to plug:
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*
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* pc // gets irq_entry
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* lr // gets lr_svc
|
|
* sp // gets sp_svc
|
|
* spsr // gets (I32_bit | PSR_SVC32_MODE)
|
|
*
|
|
*/
|
|
mov r1, #(I32_bit | PSR_SVC32_MODE)
|
|
str r1, [r0, #0] /* plug spsr */
|
|
|
|
/* Sneak into SVC mode to get sp and lr */
|
|
mrs r3, cpsr_all
|
|
bic r3, r3, #(PSR_MODE)
|
|
orr r3, r3, #(PSR_SVC32_MODE)
|
|
msr cpsr_all, r3
|
|
mov r4, lr /* snarf lr_svc */
|
|
mov r5, sp /* snarf sp_svc */
|
|
bic r3, r3, #(PSR_MODE)
|
|
orr r3, r3, #(PSR_IRQ32_MODE)
|
|
msr cpsr_all, r3
|
|
str r5, [r0, #(4*14)] /* plug sp */
|
|
str r4, [r0, #(4*15)] /* plug lr */
|
|
|
|
ldr r1, [pc, #(Lirq_entry - . - 8)]
|
|
str r1, [r0, #(4*16)] /* plug pc */
|
|
|
|
ldmfd sp!, {r1-r5}
|
|
mov pc, lr
|
|
|
|
|
|
.bss
|
|
.align 0
|
|
|
|
_ofw_ticktmp:
|
|
.space 4 * 6 /* temporary storage for 6 words of machine state */
|
|
|
|
ofwirqstk: /* hack */
|
|
.space 4096
|
|
|
|
#ifdef IRQSTATS
|
|
/* These symbols are used by vmstat */
|
|
|
|
.text
|
|
.global __intrnames
|
|
__intrnames:
|
|
.word _intrnames
|
|
|
|
.data
|
|
|
|
.globl _intrnames, _eintrnames, _intrcnt, _sintrcnt, _eintrcnt
|
|
_intrnames:
|
|
.asciz "interrupt 0 "
|
|
.asciz "interrupt 1 "
|
|
.asciz "interrupt 2 "
|
|
.asciz "interrupt 3 "
|
|
.asciz "interrupt 4 "
|
|
.asciz "interrupt 5 "
|
|
.asciz "interrupt 6 "
|
|
.asciz "interrupt 7 "
|
|
.asciz "interrupt 8 "
|
|
.asciz "interrupt 9 "
|
|
.asciz "interrupt 10 "
|
|
.asciz "interrupt 11 "
|
|
.asciz "interrupt 12 "
|
|
.asciz "interrupt 13 "
|
|
.asciz "interrupt 14 "
|
|
.asciz "interrupt 15 "
|
|
.asciz "interrupt 16 "
|
|
.asciz "interrupt 17 "
|
|
.asciz "interrupt 18 "
|
|
.asciz "interrupt 19 "
|
|
.asciz "interrupt 20 "
|
|
.asciz "interrupt 21 "
|
|
.asciz "interrupt 22 "
|
|
.asciz "interrupt 23 "
|
|
.asciz "interrupt 24 "
|
|
.asciz "interrupt 25 "
|
|
.asciz "interrupt 26 "
|
|
.asciz "interrupt 27 "
|
|
.asciz "interrupt 28 "
|
|
.asciz "interrupt 29 "
|
|
.asciz "interrupt 30 "
|
|
.asciz "interrupt 31 "
|
|
|
|
_sintrnames:
|
|
.asciz "softclock "
|
|
.asciz "softnet "
|
|
.asciz "softserial "
|
|
.asciz "softintr 3 "
|
|
.asciz "softintr 4 "
|
|
.asciz "softintr 5 "
|
|
.asciz "softintr 6 "
|
|
.asciz "softintr 7 "
|
|
.asciz "softintr 8 "
|
|
.asciz "softintr 9 "
|
|
.asciz "softintr 10 "
|
|
.asciz "softintr 11 "
|
|
.asciz "softintr 12 "
|
|
.asciz "softintr 13 "
|
|
.asciz "softintr 14 "
|
|
.asciz "softintr 15 "
|
|
.asciz "softintr 16 "
|
|
.asciz "softintr 17 "
|
|
.asciz "softintr 18 "
|
|
.asciz "softintr 19 "
|
|
.asciz "softintr 20 "
|
|
.asciz "softintr 21 "
|
|
.asciz "softintr 22 "
|
|
.asciz "softintr 23 "
|
|
.asciz "softintr 24 "
|
|
.asciz "softintr 25 "
|
|
.asciz "softintr 26 "
|
|
.asciz "softintr 27 "
|
|
.asciz "softintr 28 "
|
|
.asciz "softintr 29 "
|
|
.asciz "softintr 30 "
|
|
.asciz "softintr 31 "
|
|
_eintrnames:
|
|
|
|
.bss
|
|
.align 0
|
|
_intrcnt:
|
|
.space 32*4 /* XXX Should be linked to number of interrupts */
|
|
|
|
_sintrcnt:
|
|
.space 32*4 /* XXX Should be linked to number of interrupts */
|
|
_eintrcnt:
|
|
|
|
#else /* IRQSTATS */
|
|
/* Dummy entries to keep vmstat happy */
|
|
|
|
.text
|
|
.globl _intrnames, _eintrnames, _intrcnt, _eintrcnt
|
|
_intrnames:
|
|
.long 0
|
|
_eintrnames:
|
|
|
|
_intrcnt:
|
|
.long 0
|
|
_eintrcnt:
|
|
#endif /* IRQSTATS */
|
|
|
|
/* FIQ code */
|
|
|
|
ENTRY(fiq_setregs)
|
|
mrs r2, cpsr_all
|
|
mov r3, r2
|
|
bic r2, r2, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_FIQ32_MODE)
|
|
msr cpsr_all, r2
|
|
|
|
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
|
|
ldr r9, [r0, #FH_R9]
|
|
ldr r10, [r0, #FH_R10]
|
|
ldr r11, [r0, #FH_R11]
|
|
ldr r12, [r0, #FH_R12]
|
|
ldr r13, [r0, #FH_R13]
|
|
|
|
msr cpsr_all, r3 /* Back to old mode */
|
|
|
|
mov pc, lr /* Exit */
|
|
|
|
ENTRY(fiq_getregs)
|
|
mrs r2, cpsr_all
|
|
mov r3, r2
|
|
bic r2, r2, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_FIQ32_MODE)
|
|
msr cpsr_all, r2
|
|
|
|
str r8, [r0, #FH_R8] /* Update FIQ registers*/
|
|
str r9, [r0, #FH_R9]
|
|
str r10, [r0, #FH_R10]
|
|
str r11, [r0, #FH_R11]
|
|
str r12, [r0, #FH_R12]
|
|
str r13, [r0, #FH_R13]
|
|
|
|
msr cpsr_all, r3 /* Back to old mode */
|
|
|
|
mov pc, lr /* Exit */
|
|
|
|
/* End of irq.S */
|