241 lines
7.4 KiB
C
241 lines
7.4 KiB
C
/* $NetBSD: memcreg.h,v 1.2 2002/03/24 23:37:43 bjh21 Exp $ */
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/*-
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* Copyright (c) 1997, 1998 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* memcreg.h - Acorn/ARM MEMC (Anna/VC2304/VL2304/MEMC1A/VL2304A/VL86C110/VY86C110)
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* registers
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*/
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#ifndef _ARM26_MEMCREG_H
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#define _ARM26_MEMCREG_H
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/*
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* Accessing the MEMC is a little odd. It's not connected to the data
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* bus, so the register and the new value are coded into an address.
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* Thus, to set a register, OR together the register specifier and the
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* new value, and write any word to the resultant address.
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*/
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#define MEMC_WRITE(value) *(volatile u_int32_t *)value = 0
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/*
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* This information is mostly derived from:
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* MEMC Datasheet
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* Published by Acorn Computers Limited.
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* Part no 0460,019
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* Issue No 1.0
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* 30 September 1986
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* ISBN 1 85250 025 6
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*
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* Thanks must go to Jeanette Draper at ARM Ltd
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* <jeanette.draper@arm.com> for finding it for me.
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*
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* Information on master/slave MEMCs came from Tony Duell
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* <ard@p850ug1.demon.co.uk>, who has a copy of the MEMC1A data
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* sheet and might photocopy it for me one day.
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*/
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/* General memory-map layout provided by MEMC */
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#define MEMC_PHYS_BASE ((caddr_t)0x02000000)
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#define MEMC_IO_BASE ((caddr_t)0x03000000)
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#define MEMC_VIDC_BASE ((caddr_t)0x03400000)
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#define MEMC_ROM_LOW_BASE ((caddr_t)0x03400000)
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#define MEMC_ROM_HIGH_BASE ((caddr_t)0x03800000)
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/*
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* Each MEMC can manage 4Mb in 128 pages. The memory map only has
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* space for 16Mb of physical RAM.
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*/
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#define MEMC_MAX_PHYSPAGES 512
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/*
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* DMA address generator control registers. Addresses (>>4) go in
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* bits 2-16, and must thus be in the bottom 512k of physical RAM.
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*/
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#define MEMC_DMA_MAX 0x00080000
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/* Video */
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#define MEMC_VINIT 0x03600000
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#define MEMC_VSTART 0x03620000
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#define MEMC_VEND 0x03640000
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/* Cursor */
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#define MEMC_CINIT 0x03660000
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/* Sound */
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#define MEMC_SSTARTN 0x03680000
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#define MEMC_SENDN 0x036A0000
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#define MEMC_SPTR 0x036C0000
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#define MEMC_SET_PTR(reg,addr) (reg | (addr >> 2))
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/* MEMC control register (sec 6.5) */
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#define MEMC_CONTROL 0x036E0000
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/* Page size */
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#define MEMC_CTL_PGSZ_MASK 0x0000000C
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#define MEMC_CTL_PGSZ_4K 0x00000000
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#define MEMC_CTL_PGSZ_8K 0x00000004
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#define MEMC_CTL_PGSZ_16K 0x00000008
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#define MEMC_CTL_PGSZ_32K 0x0000000C
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/* ROM speeds; low and high banks, relative to RAM speed */
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#define MEMC_CTL_LROMSPD_MASK 0x00000030
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#define MEMC_CTL_LROMSPD_4N 0x00000000
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#define MEMC_CTL_LROMSPD_3N 0x00000010
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#define MEMC_CTL_LROMSPD_2N 0x00000020
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#define MEMC_CTL_LROMSPD_PAGED 0x00000030
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#define MEMC_CTL_HROMSPD_MASK 0x000000C0
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#define MEMC_CTL_HROMSPD_4N 0x00000000
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#define MEMC_CTL_HROMSPD_3N 0x00000040
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#define MEMC_CTL_HROMSPD_2N 0x00000080
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#define MEMC_CTL_HROMSPD_PAGED 0x000000C0
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/* DRAM refresh control */
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#define MEMC_CTL_RFRSH_MASK 0x00000300
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#define MEMC_CTL_RFRSH_NONE 0x00000000
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#define MEMC_CTL_RFRSH_FLYBACK 0x00000100
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#define MEMC_CTL_RFRSH_CONTIN 0x00000300
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/* Enable video DMA */
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#define MEMC_CTL_VIDEODMA 0x00000400
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/* Enable sound DMA */
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#define MEMC_CTL_SOUNDDMA 0x00000800
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/* Operating System Mode Select */
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#define MEMC_CTL_OSMODE 0x00001000
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/* Test mode */
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/* This should never be set in a running system */
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#define MEMC_CTL_TESTMODE 0x00002000
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/*
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* Address translation control
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*/
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/* Absolute address of translation table */
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#define MEMC_TRANS_BASE 0x03800000
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/*
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* MEMC translation entries are painful, and vary with the page size
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* in use. Here, ppn is the physical page number, lpn is the logical
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* page number and ppl is the page protection level.
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*
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* The list of transformations at the start of each macro is copied
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* verbatim from the MEMC datasheet (Figure 5) with the exception of
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* the entries for PPN[7] and PPN[8]. In dual-MEMC situations, PPN[7]
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* selects between master and slave MEMCs, and is mapped to A[7] whatever
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* the page size (though Acorn machines always use 32k pages with dual
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* MEMCs). The Archimedes 540 can have up to 16Mb of RAM, and arranges
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* this by having several address lines go through PALs on their way to the
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* MEMCs. The upshot of this is that for the purposes of setting the
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* translation tables, PPN[8] maps to A[12]. The A540 always has 32kb pages.
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*/
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/* Page protection levels (data sheet section 6.6) */
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/*-
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* PPL
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* Mode 00 01 10 11
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* SVC R/W R/W R/W R/W
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* OS R/W R/W R R
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* User R/W R - -
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*/
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#define MEMC_PPL_RDWR 0
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#define MEMC_PPL_RDONLY 1
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#define MEMC_PPL_NOACCESS 2
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/*-
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* 4k pages:
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* PPN[7] -> A[7] (MEMC1a)
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* PPN[6:0] -> A[6:0]
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* PPL[1:0] -> A[9:8]
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* LPN[12:11] -> A[11:10]
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* LPN[10:0] -> A[22:12]
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*/
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#define MEMC_TRANS_ENTRY_4K(ppn, lpn, ppl) \
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(MEMC_TRANS_BASE | \
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((ppn) & 0xff) | \
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((ppl) & 0x3) << 8 | \
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((lpn) & 0x7ff) << 12 | \
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((lpn) & 0x1800) >> 1)
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/*-
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* 8k pages:
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* PPN[7] -> A[7] (MEMC1a)
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* PPN[6] -> A[0]
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* PPN[5:0] -> A[6:1]
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* PPL[1:0] -> A[9:8]
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* LPN[11:10] -> A[11:10]
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* LPN[9:0] -> A[22:13]
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*/
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#define MEMC_TRANS_ENTRY_8K(ppn, lpn, ppl) \
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(MEMC_TRANS_BASE | \
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((ppn) & 0x80) | \
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((ppn) & 0x40) >> 6 | \
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((ppn) & 0x3f) << 1 | \
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((ppl) & 0x3) << 8 | \
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((lpn) & 0xc00)) | \
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((lpn) & 0x3ff) << 13)
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/*-
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* 16k pages:
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* PPN[7] -> A[7] (MEMC1a)
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* PPN[6:5] -> A[1:0]
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* PPN[4:0] -> A[6:2]
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* PPL[1:0] -> A[9:8]
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* LPN[10:9] -> A[11:10]
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* LPN[9:0] -> A[22:14]
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*/
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#define MEMC_TRANS_ENTRY_16K(ppn, lpn, ppl) \
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(MEMC_TRANS_BASE | \
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((ppn) & 0x80) | \
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((ppn) & 0x60) >> 5 | \
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((ppn) & 0x1f) << 2 | \
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((ppl) & 0x3) << 8 | \
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((lpn) & 0x600) << 1 | \
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((lpn) & 0x1ff) << 14)
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/*-
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* 32k pages (here, the MEMC descends into madness...):
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* PPN[8] -> A[12] (A540)
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* PPN[7] -> A[7] (MEMC1a)
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* PPN[6] -> A[1]
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* PPN[5] -> A[2]
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* PPN[4] -> A[0]
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* PPN[3:0] -> A[6:3]
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* PPL[1:0] -> A[9:8]
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* LPN[9:8] -> A[11:10]
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* LPN[7:0] -> A[22:15]
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*/
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#define MEMC_TRANS_ENTRY_32K(ppn, lpn, ppl) \
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(MEMC_TRANS_BASE | \
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((ppn) & 0x100) << 4 | \
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((ppn) & 0x80) | \
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((ppn) & 0x40) >> 5 | \
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((ppn) & 0x20) >> 3 | \
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((ppn) & 0x10) >> 4 | \
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((ppn) & 0x0f) << 3 | \
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((ppl) & 0x3) << 8 | \
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((lpn) & 0x300) << 2 | \
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((lpn) & 0x0ff) << 15)
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#endif
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