261 lines
7.5 KiB
C
261 lines
7.5 KiB
C
/* $NetBSD: wdc_spd.c,v 1.25 2009/03/18 10:22:33 cegger Exp $ */
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/*-
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* Copyright (c) 2001, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: wdc_spd.c,v 1.25 2009/03/18 10:22:33 cegger Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#define __read_1(a) \
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({ \
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u_int32_t ra_ = (a); \
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u_int8_t r = (*(volatile u_int8_t *)ra_); \
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\
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if (ra_ == 0xb400004e) /* (wdc)STAT LED off */ \
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SPD_LED_OFF(); \
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\
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(r); \
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})
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#define __write_1(a, v) \
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{ \
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u_int32_t wa_ = (a); \
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(*(volatile u_int8_t *)wa_) = (v); \
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\
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if (wa_ == 0xb400004e) /* (wdc)CMD LED on */ \
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SPD_LED_ON(); \
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}
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#define _PLAYSTATION2_BUS_SPACE_PRIVATE
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#include <machine/bus.h>
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcvar.h>
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#include <playstation2/ee/eevar.h>
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#include <playstation2/dev/spdvar.h>
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#include <playstation2/dev/spdreg.h>
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#define WDC_SPD_HDD_AUXREG_OFFSET 0x1c
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struct wdc_spd_softc {
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struct wdc_softc sc_wdcdev;
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struct ata_channel *sc_chanlist[1];
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struct ata_channel sc_channel;
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struct ata_queue sc_chqueue;
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struct wdc_regs sc_wdc_regs;
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void *sc_ih;
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};
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#ifdef DEBUG
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#define STATIC
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#else
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#define STATIC static
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#endif
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STATIC int wdc_spd_match(device_t, cfdata_t, void *);
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STATIC void wdc_spd_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(wdc_spd, sizeof (struct wdc_spd_softc),
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wdc_spd_match, wdc_spd_attach, NULL, NULL);
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extern struct cfdriver wdc_cd;
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STATIC void __wdc_spd_enable(void);
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STATIC void __wdc_spd_disable(void) __attribute__((__unused__));
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STATIC void __wdc_spd_bus_space(struct ata_channel *);
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/*
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* wdc register is 16 bit wide.
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*/
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#define VADDR(h, o) ((h) + (o))
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_BUS_SPACE_READ(_wdc_spd, 1, 8)
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_BUS_SPACE_READ(_wdc_spd, 2, 16)
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_BUS_SPACE_READ_MULTI(_wdc_spd, 1, 8)
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_BUS_SPACE_READ_MULTI(_wdc_spd, 2, 16)
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_BUS_SPACE_READ_REGION(_wdc_spd, 1, 8)
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_BUS_SPACE_READ_REGION(_wdc_spd, 2, 16)
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_BUS_SPACE_WRITE(_wdc_spd, 1, 8)
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_BUS_SPACE_WRITE(_wdc_spd, 2, 16)
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_BUS_SPACE_WRITE_MULTI(_wdc_spd, 1, 8)
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_BUS_SPACE_WRITE_MULTI(_wdc_spd, 2, 16)
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_BUS_SPACE_WRITE_REGION(_wdc_spd, 1, 8)
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_BUS_SPACE_WRITE_REGION(_wdc_spd, 2, 16)
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_BUS_SPACE_SET_MULTI(_wdc_spd, 1, 8)
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_BUS_SPACE_SET_MULTI(_wdc_spd, 2, 16)
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_BUS_SPACE_SET_REGION(_wdc_spd, 1, 8)
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_BUS_SPACE_SET_REGION(_wdc_spd, 2, 16)
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_BUS_SPACE_COPY_REGION(_wdc_spd, 1, 8)
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_BUS_SPACE_COPY_REGION(_wdc_spd, 2, 16)
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#undef VADDR
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STATIC const struct playstation2_bus_space _wdc_spd_space = {
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pbs_map : _BUS_SPACE_NO_MAP,
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pbs_unmap : _BUS_SPACE_NO_UNMAP,
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pbs_subregion : _BUS_SPACE_NO_SUBREGION,
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pbs_alloc : _BUS_SPACE_NO_ALLOC,
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pbs_free : _BUS_SPACE_NO_FREE,
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pbs_vaddr : _BUS_SPACE_NO_VADDR,
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pbs_r_1 : _wdc_spd_read_1,
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pbs_r_2 : _wdc_spd_read_2,
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pbs_r_4 : _BUS_SPACE_NO_READ(4, 32),
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pbs_r_8 : _BUS_SPACE_NO_READ(8, 64),
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pbs_rm_1 : _wdc_spd_read_multi_1,
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pbs_rm_2 : _wdc_spd_read_multi_2,
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pbs_rm_4 : _BUS_SPACE_NO_READ_MULTI(4, 32),
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pbs_rm_8 : _BUS_SPACE_NO_READ_MULTI(8, 64),
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pbs_rr_1 : _wdc_spd_read_region_1,
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pbs_rr_2 : _wdc_spd_read_region_2,
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pbs_rr_4 : _BUS_SPACE_NO_READ_REGION(4, 32),
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pbs_rr_8 : _BUS_SPACE_NO_READ_REGION(8, 64),
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pbs_w_1 : _wdc_spd_write_1,
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pbs_w_2 : _wdc_spd_write_2,
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pbs_w_4 : _BUS_SPACE_NO_WRITE(4, 32),
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pbs_w_8 : _BUS_SPACE_NO_WRITE(8, 64),
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pbs_wm_1 : _wdc_spd_write_multi_1,
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pbs_wm_2 : _wdc_spd_write_multi_2,
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pbs_wm_4 : _BUS_SPACE_NO_WRITE_MULTI(4, 32),
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pbs_wm_8 : _BUS_SPACE_NO_WRITE_MULTI(8, 64),
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pbs_wr_1 : _wdc_spd_write_region_1,
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pbs_wr_2 : _wdc_spd_write_region_2,
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pbs_wr_4 : _BUS_SPACE_NO_WRITE_REGION(4, 32),
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pbs_wr_8 : _BUS_SPACE_NO_WRITE_REGION(8, 64),
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pbs_sm_1 : _wdc_spd_set_multi_1,
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pbs_sm_2 : _wdc_spd_set_multi_2,
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pbs_sm_4 : _BUS_SPACE_NO_SET_MULTI(4, 32),
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pbs_sm_8 : _BUS_SPACE_NO_SET_MULTI(8, 64),
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pbs_sr_1 : _wdc_spd_set_region_1,
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pbs_sr_2 : _wdc_spd_set_region_2,
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pbs_sr_4 : _BUS_SPACE_NO_SET_REGION(4, 32),
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pbs_sr_8 : _BUS_SPACE_NO_SET_REGION(8, 64),
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pbs_c_1 : _wdc_spd_copy_region_1,
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pbs_c_2 : _wdc_spd_copy_region_2,
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pbs_c_4 : _BUS_SPACE_NO_COPY_REGION(4, 32),
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pbs_c_8 : _BUS_SPACE_NO_COPY_REGION(8, 64),
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};
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int
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wdc_spd_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct spd_attach_args *spa = aux;
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struct ata_channel ch;
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struct wdc_softc wdc;
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struct wdc_regs wdr;
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int i, result;
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if (spa->spa_slot != SPD_HDD)
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return (0);
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memset(&wdc, 0, sizeof(wdc));
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memset(&ch, 0, sizeof(ch));
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ch.ch_atac = &wdc.sc_atac;
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wdc.regs = &wdr;
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__wdc_spd_bus_space(&ch);
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for (i = 0, result = 0; i < 8; i++) { /* 8 sec */
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if (result == 0)
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result = wdcprobe(&ch);
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delay(1000000);
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}
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return (result);
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}
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void
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wdc_spd_attach(device_t parent, device_t self, void *aux)
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{
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struct spd_attach_args *spa = aux;
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struct wdc_spd_softc *sc = device_private(self);
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struct wdc_softc *wdc = &sc->sc_wdcdev;
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struct ata_channel *ch = &sc->sc_channel;
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aprint_normal(": %s\n", spa->spa_product_name);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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sc->sc_wdcdev.regs = &sc->sc_wdc_regs;
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wdc->sc_atac.atac_cap =
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ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_DATA16;
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wdc->sc_atac.atac_pio_cap = 0;
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sc->sc_chanlist[0] = &sc->sc_channel;
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wdc->sc_atac.atac_channels = sc->sc_chanlist;
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wdc->sc_atac.atac_nchannels = 1;
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ch->ch_channel = 0;
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ch->ch_atac = &sc->sc_wdcdev.sc_atac;
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ch->ch_queue = &sc->sc_chqueue;
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ch->ch_ndrive = 2;
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__wdc_spd_bus_space(ch);
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spd_intr_establish(SPD_HDD, wdcintr, &sc->sc_channel);
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__wdc_spd_enable();
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wdcattach(&sc->sc_channel);
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}
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void
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__wdc_spd_bus_space(struct ata_channel *ch)
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{
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(ch);
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int i;
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wdr->cmd_iot = &_wdc_spd_space;
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for (i = 0; i < 8; i++)
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wdr->cmd_iohs[i] = SPD_HDD_IO_BASE + i * 2; /* wdc register is 16 bit wide. */
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wdc_init_shadow_regs(ch);
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wdr->ctl_iot = &_wdc_spd_space;
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wdr->ctl_ioh = SPD_HDD_IO_BASE + WDC_SPD_HDD_AUXREG_OFFSET;
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = SPD_HDD_IO_BASE;
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}
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void
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__wdc_spd_enable(void)
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{
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u_int16_t r;
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r = _reg_read_2(SPD_INTR_ENABLE_REG16);
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r |= SPD_INTR_HDD;
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_reg_write_2(SPD_INTR_ENABLE_REG16, r);
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}
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void
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__wdc_spd_disable(void)
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{
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u_int16_t r;
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r = _reg_read_2(SPD_INTR_ENABLE_REG16);
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r &= ~SPD_INTR_HDD;
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_reg_write_2(SPD_INTR_ENABLE_REG16, r);
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}
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