493 lines
13 KiB
C
493 lines
13 KiB
C
/* $NetBSD: marvell_intr.h,v 1.15 2008/04/28 20:23:32 martin Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVPPPC_INTR_H_
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#define _MVPPPC_INTR_H_
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#include <powerpc/psl.h>
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#include <powerpc/frame.h>
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/*
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* Interrupt Priority Levels
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*/
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#define IPL_NONE 0 /* nothing */
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#define IPL_SOFTCLOCK 1 /* timeouts */
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#define IPL_SOFTBIO 2 /* block I/O */
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#define IPL_SOFTNET 3 /* protocol stacks */
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#define IPL_SOFTSERIAL 4 /* serial */
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#define IPL_VM 12 /* memory allocation */
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#define IPL_SCHED 14 /* clock */
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#define IPL_HIGH 15 /* everything */
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#define NIPL 16
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#define IPL_PRIMASK 0xf
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#define IPL_EE 0x10 /* enable external interrupts on splx */
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#define IST_SOFT 4 /* software-triggered */
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#define IST_CLOCK 5 /* exclusive for clock */
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#define NIST 6
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#if !defined(_LOCORE) && defined(_KERNEL)
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#define CLKF_BASEPRI(frame) ((frame)->pri == IPL_NONE)
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/*
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* we support 128 IRQs:
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* 96 (ICU_LEN) hard interrupt IRQs:
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* - 64 Main Cause IRQs,
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* - 32 GPP IRQs,
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* and 32 softint IRQs
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*/
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#define ICU_LEN 96 /* number of HW IRQs */
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#define IRQ_GPP_BASE 64 /* base of GPP IRQs */
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#define IRQ_GPP_SUM (32+24) /* GPP[7..0] interrupt */ /* XXX */
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#define NIRQ 128 /* total # of HW IRQs */
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#define IMASK_ICU_LO 0
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#define IMASK_ICU_HI 1
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#define IMASK_ICU_GPP 2
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#define IMASK_SOFTINT 3
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#define IMASK_WORDSHIFT 5 /* log2(32) */
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#define IMASK_BITMASK ~((~0) << IMASK_WORDSHIFT)
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#define IRQ_IS_GPP(irq) ((irq >= IRQ_GPP_BASE) && (irq < ICU_LEN))
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/*
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* interrupt mask bit vector
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*/
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typedef struct {
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u_int32_t bits[4];
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} imask_t __attribute__ ((aligned(16)));
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static inline void imask_zero(imask_t *);
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static inline void imask_zero_v(volatile imask_t *);
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static inline void imask_dup_v(imask_t *, const volatile imask_t *);
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static inline void imask_and(imask_t *, const imask_t *);
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static inline void imask_andnot_v(volatile imask_t *, const imask_t *);
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static inline void imask_andnot_icu_vv(volatile imask_t *, const volatile imask_t *);
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static inline int imask_empty(const imask_t *);
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static inline void imask_orbit(imask_t *, int);
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static inline void imask_orbit_v(volatile imask_t *, int);
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static inline void imask_clrbit(imask_t *, int);
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static inline void imask_clrbit_v(volatile imask_t *, int);
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static inline u_int32_t imask_andbit_v(const volatile imask_t *, int);
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static inline int imask_test_v(const volatile imask_t *, const imask_t *);
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static inline void
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imask_zero(imask_t *idp)
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{
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idp->bits[IMASK_ICU_LO] = 0;
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idp->bits[IMASK_ICU_HI] = 0;
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idp->bits[IMASK_ICU_GPP] = 0;
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idp->bits[IMASK_SOFTINT] = 0;
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}
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static inline void
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imask_zero_v(volatile imask_t *idp)
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{
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idp->bits[IMASK_ICU_LO] = 0;
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idp->bits[IMASK_ICU_HI] = 0;
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idp->bits[IMASK_ICU_GPP] = 0;
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idp->bits[IMASK_SOFTINT] = 0;
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}
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static inline void
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imask_dup_v(imask_t *idp, const volatile imask_t *isp)
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{
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*idp = *isp;
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}
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static inline void
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imask_and(imask_t *idp, const imask_t *isp)
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{
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idp->bits[IMASK_ICU_LO] &= isp->bits[IMASK_ICU_LO];
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idp->bits[IMASK_ICU_HI] &= isp->bits[IMASK_ICU_HI];
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idp->bits[IMASK_ICU_GPP] &= isp->bits[IMASK_ICU_GPP];
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idp->bits[IMASK_SOFTINT] &= isp->bits[IMASK_SOFTINT];
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}
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static inline void
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imask_andnot_v(volatile imask_t *idp, const imask_t *isp)
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{
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idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO];
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idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI];
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idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP];
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idp->bits[IMASK_SOFTINT] &= ~isp->bits[IMASK_SOFTINT];
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}
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static inline void
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imask_andnot_icu_vv(volatile imask_t *idp, const volatile imask_t *isp)
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{
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idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO];
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idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI];
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idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP];
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}
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static inline int
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imask_empty(const imask_t *isp)
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{
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return (! (isp->bits[IMASK_ICU_LO] | isp->bits[IMASK_ICU_HI] |
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isp->bits[IMASK_ICU_GPP]| isp->bits[IMASK_SOFTINT]));
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}
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static inline void
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imask_orbit(imask_t *idp, int bitno)
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{
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idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK));
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}
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static inline void
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imask_orbit_v(volatile imask_t *idp, int bitno)
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{
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idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK));
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}
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static inline void
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imask_clrbit(imask_t *idp, int bitno)
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{
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idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK));
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}
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static inline void
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imask_clrbit_v(volatile imask_t *idp, int bitno)
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{
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idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK));
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}
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static inline u_int32_t
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imask_andbit_v(const volatile imask_t *idp, int bitno)
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{
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return idp->bits[bitno>>IMASK_WORDSHIFT] & (1 << (bitno&IMASK_BITMASK));
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}
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static inline int
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imask_test_v(const volatile imask_t *idp, const imask_t *isp)
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{
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return ((idp->bits[IMASK_ICU_LO] & isp->bits[IMASK_ICU_LO]) ||
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(idp->bits[IMASK_ICU_HI] & isp->bits[IMASK_ICU_HI]) ||
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(idp->bits[IMASK_ICU_GPP] & isp->bits[IMASK_ICU_GPP])||
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(idp->bits[IMASK_SOFTINT] & isp->bits[IMASK_SOFTINT]));
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}
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#ifdef EXT_INTR_STATS
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/*
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* ISR timing stats
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*/
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typedef struct ext_intr_hist {
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u_int64_t tcause;
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u_int64_t tcommit;
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u_int64_t tstart;
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u_int64_t tfin;
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} ext_intr_hist_t __attribute__ ((aligned(32)));
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typedef struct ext_intr_stat {
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struct ext_intr_hist *histp;
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unsigned int histix;
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u_int64_t cnt;
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u_int64_t sum;
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u_int64_t min;
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u_int64_t max;
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u_int64_t pnd;
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u_int64_t borrowed;
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struct ext_intr_stat *save;
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unsigned long preempted[NIRQ]; /* XXX */
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} ext_intr_stat_t __attribute__ ((aligned(32)));
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extern int intr_depth_max;
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extern int ext_intr_stats_enb;
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extern ext_intr_stat_t ext_intr_stats[];
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extern ext_intr_stat_t *ext_intr_statp;
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extern void ext_intr_stats_init __P((void));
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extern void ext_intr_stats_cause
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__P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
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extern void ext_intr_stats_pend
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__P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
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extern void ext_intr_stats_commit __P((imask_t *));
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extern void ext_intr_stats_commit_m __P((imask_t *));
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extern void ext_intr_stats_commit_irq __P((u_int));
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extern u_int64_t ext_intr_stats_pre __P((int));
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extern void ext_intr_stats_post __P((int, u_int64_t));
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#define EXT_INTR_STATS_INIT() ext_intr_stats_init()
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#define EXT_INTR_STATS_CAUSE(l, h, g, s) ext_intr_stats_cause(l, h, g, s)
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#define EXT_INTR_STATS_COMMIT_M(m) ext_intr_stats_commit_m(m)
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#define EXT_INTR_STATS_COMMIT_IRQ(i) ext_intr_stats_commit_irq(i)
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#define EXT_INTR_STATS_DECL(t) u_int64_t t
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#define EXT_INTR_STATS_PRE(i, t) t = ext_intr_stats_pre(i)
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#define EXT_INTR_STATS_POST(i, t) ext_intr_stats_post(i, t)
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#define EXT_INTR_STATS_PEND(l, h, g, s) ext_intr_stats_pend(l, h, g, s)
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#define EXT_INTR_STATS_PEND_IRQ(i) ext_intr_stats[i].pnd++
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#define EXT_INTR_STATS_DEPTH() \
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intr_depth_max = (intr_depth > intr_depth_max) ? \
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intr_depth : intr_depth_max
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#else /* EXT_INTR_STATS */
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#define EXT_INTR_STATS_INIT()
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#define EXT_INTR_STATS_CAUSE(l, h, g, s)
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#define EXT_INTR_STATS_COMMIT_M(m)
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#define EXT_INTR_STATS_COMMIT_IRQ(i)
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#define EXT_INTR_STATS_DECL(t)
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#define EXT_INTR_STATS_PRE(irq, t)
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#define EXT_INTR_STATS_POST(i, t)
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#define EXT_INTR_STATS_PEND(l, h, g, s)
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#define EXT_INTR_STATS_PEND_IRQ(i)
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#define EXT_INTR_STATS_DEPTH()
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#endif /* EXT_INTR_STATS */
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#ifdef SPL_STATS
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typedef struct spl_hist {
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int level;
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void *addr;
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u_int64_t time;
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} spl_hist_t;
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extern void spl_stats_init();
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extern void spl_stats_log();
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extern unsigned int spl_stats_enb;
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#define SPL_STATS_INIT() spl_stats_init()
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#define SPL_STATS_LOG(ipl, cc) spl_stats_log((ipl), (cc))
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#else
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#define SPL_STATS_INIT()
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#define SPL_STATS_LOG(ipl, cc)
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#endif /* SPL_STATS */
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void intr_dispatch __P((void));
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#ifdef SPL_INLINE
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static inline int splraise __P((int));
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static inline int spllower __P((int));
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static inline void splx __P((int));
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#else
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extern int splraise __P((int));
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extern int spllower __P((int));
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extern void splx __P((int));
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#endif
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extern volatile int tickspending;
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extern volatile imask_t ipending;
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extern imask_t imask[];
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/*
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* inlines for manipulating PSL_EE
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*/
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static inline void
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extintr_restore(register_t omsr)
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{
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__asm volatile ("sync; mtmsr %0;" :: "r"(omsr));
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}
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static inline register_t
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extintr_enable(void)
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{
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register_t omsr;
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__asm volatile("sync;");
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__asm volatile("mfmsr %0;" : "=r"(omsr));
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__asm volatile("mtmsr %0;" :: "r"(omsr | PSL_EE));
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return omsr;
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}
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static inline register_t
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extintr_disable(void)
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{
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register_t omsr;
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__asm volatile("mfmsr %0;" : "=r"(omsr));
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__asm volatile("mtmsr %0;" :: "r"(omsr & ~PSL_EE));
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__asm volatile("isync;");
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return omsr;
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}
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#ifdef SPL_INLINE
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static inline int
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splraise(int ncpl)
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{
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int ocpl;
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register_t omsr;
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omsr = extintr_disable();
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ocpl = cpl;
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if (ncpl > cpl) {
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SPL_STATS_LOG(ncpl, 0);
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cpl = ncpl;
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if ((ncpl == IPL_HIGH) && ((omsr & PSL_EE) != 0)) {
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/* leave external interrupts disabled */
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return (ocpl | IPL_EE);
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}
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}
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extintr_restore(omsr);
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return (ocpl);
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}
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static inline void
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splx(int xcpl)
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{
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imask_t *ncplp;
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register_t omsr;
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int ncpl = xcpl & IPL_PRIMASK;
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ncplp = &imask[ncpl];
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omsr = extintr_disable();
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if (ncpl < cpl) {
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cpl = ncpl;
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SPL_STATS_LOG(ncpl, 0);
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if (imask_test_v(&ipending, ncplp))
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intr_dispatch();
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}
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if (xcpl & IPL_EE)
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omsr |= PSL_EE;
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extintr_restore(omsr);
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}
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static inline int
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spllower(int ncpl)
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{
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int ocpl;
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imask_t *ncplp;
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register_t omsr;
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ncpl &= IPL_PRIMASK;
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ncplp = &imask[ncpl];
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omsr = extintr_disable();
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ocpl = cpl;
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cpl = ncpl;
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SPL_STATS_LOG(ncpl, 0);
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#ifdef EXT_INTR_STATS
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ext_intr_statp = 0;
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#endif
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if (imask_test_v(&ipending, ncplp))
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intr_dispatch();
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if (ncpl < IPL_HIGH)
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omsr |= PSL_EE;
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extintr_restore(omsr);
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return (ocpl);
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}
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#endif /* SPL_INLINE */
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/*
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* Soft interrupt IRQs
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* see also intrnames[] in locore.S
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*/
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#define SIR_BASE (NIRQ-32)
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#define SIXBIT(ipl) ((ipl) - SIR_BASE) /* XXX rennovate later */
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#define SIR_SOFTCLOCK (NIRQ-5)
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#define SIR_CLOCK SIXBIT(SIR_SOFTCLOCK) /* XXX rennovate later */
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#define SIR_SOFTNET (NIRQ-4)
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#define SIR_SOFTBIO (NIRQ-3)
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#define SIR_SOFTSERIAL (NIRQ-2)
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#define SIR_HWCLOCK (NIRQ-1)
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#define SPL_CLOCK SIXBIT(SIR_HWCLOCK) /* XXX rennovate later */
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#define SIR_RES ~(SIBIT(SIR_SOFTCLOCK)|\
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SIBIT(SIR_SOFTNET)|\
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SIBIT(SIR_SOFTBIO)|\
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SIBIT(SIR_SOFTSERIAL)|\
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SIBIT(SIR_HWCLOCK))
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struct intrhand;
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/*
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* Miscellaneous
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*/
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#define spl0() spllower(IPL_NONE)
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typedef int ipl_t;
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typedef struct {
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ipl_t _ipl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._ipl = ipl};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return splraise(icookie._ipl);
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}
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#include <sys/spl.h>
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#define SIBIT(ipl) (1 << ((ipl) - SIR_BASE))
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void *intr_establish(int, int, int, int (*)(void *), void *);
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void intr_disestablish(void *);
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void init_interrupt(void);
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const char * intr_typename(int);
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const char * intr_string(int);
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const struct evcnt * intr_evcnt(int);
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void ext_intr(struct intrframe *);
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/* the following are needed to compile until this port is properly
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* converted to ppcoea-rennovation.
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*/
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void genppc_cpu_configure(void);
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void strayintr(int);
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/*
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* defines for indexing intrcnt
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*/
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#define CNT_IRQ0 0
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#define CNT_CLOCK SIR_HWCLOCK
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#define CNT_SOFTCLOCK SIR_SOFTCLOCK
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#define CNT_SOFTNET SIR_NET
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#define CNT_SOFTSERIAL SIR_SOFTSERIAL
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#define CNT_SOFTBIO SIR_BIO
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#endif /* !_LOCORE */
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#endif /* _MVPPPC_INTR_H_ */
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