370 lines
8.3 KiB
C
370 lines
8.3 KiB
C
/* $NetBSD: iq80310_timer.c,v 1.11 2002/04/14 19:47:03 thorpej Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Timer/clock support for the Intel IQ80310.
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*
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* The IQ80310 has a 22-bit reloadable timer implemented in the CPLD.
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* We use it to provide a hardclock interrupt. There is no RTC on
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* the IQ80310.
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*
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* The timer uses the SPCI clock. The timer uses the 33MHz clock by
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* reading the SPCI_66EN signal and dividing the clock if necessary.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <arm/cpufunc.h>
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#include <evbarm/iq80310/iq80310reg.h>
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#include <evbarm/iq80310/iq80310var.h>
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#include <evbarm/iq80310/obiovar.h>
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/*
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* Some IQ80310-based designs have fewer bits in the timer counter.
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* Deal with them here.
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*/
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#if defined(IOP310_TEAMASA_NPWR)
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#define COUNTER_MASK 0x0007ffff
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#else /* Default to stock IQ80310 */
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#define COUNTER_MASK 0x003fffff
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#endif /* list of IQ80310-based designs */
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#define COUNTS_PER_SEC 33000000 /* 33MHz */
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#define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
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static void *clock_ih;
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static uint32_t counts_per_hz;
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int clockhandler(void *);
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static __inline void
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timer_enable(uint8_t bit)
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{
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CPLD_WRITE(IQ80310_TIMER_ENABLE,
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CPLD_READ(IQ80310_TIMER_ENABLE) | bit);
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}
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static __inline void
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timer_disable(uint8_t bit)
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{
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CPLD_WRITE(IQ80310_TIMER_ENABLE,
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CPLD_READ(IQ80310_TIMER_ENABLE) & ~bit);
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}
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static __inline uint32_t
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timer_read(void)
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{
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uint32_t rv;
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uint8_t la0, la1, la2, la3;
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/*
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* First read latches count.
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*
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* From RedBoot: harware bug that causes invalid counts to be
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* latched. The loop appears to work around the problem.
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*/
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do {
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la0 = CPLD_READ(IQ80310_TIMER_LA0);
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} while (la0 == 0);
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la1 = CPLD_READ(IQ80310_TIMER_LA1);
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la2 = CPLD_READ(IQ80310_TIMER_LA2);
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la3 = CPLD_READ(IQ80310_TIMER_LA3);
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rv = ((la0 & 0x40) >> 1) | (la0 & 0x1f);
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rv |= (((la1 & 0x40) >> 1) | (la1 & 0x1f)) << 6;
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rv |= (((la2 & 0x40) >> 1) | (la2 & 0x1f)) << 12;
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rv |= (la3 & 0x0f) << 18;
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return (rv);
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}
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static __inline void
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timer_write(uint32_t x)
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{
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KASSERT((x & COUNTER_MASK) == x);
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CPLD_WRITE(IQ80310_TIMER_LA0, x & 0xff);
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CPLD_WRITE(IQ80310_TIMER_LA1, (x >> 8) & 0xff);
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CPLD_WRITE(IQ80310_TIMER_LA2, (x >> 16) & 0x3f);
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}
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/*
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* iq80310_calibrate_delay:
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*
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* Calibrate the delay loop.
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*/
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void
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iq80310_calibrate_delay(void)
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{
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/*
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* We'll use the CPLD timer for delay(), as well. We go
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* ahead and start it up now, just don't enable interrupts
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* until cpu_initclocks().
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*
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* Just use hz=100 for now -- we'll adjust it, if necessary,
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* in cpu_initclocks().
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*/
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counts_per_hz = COUNTS_PER_SEC / 100;
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timer_disable(TIMER_ENABLE_INTEN);
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timer_disable(TIMER_ENABLE_EN);
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timer_write(counts_per_hz);
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timer_enable(TIMER_ENABLE_EN);
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}
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/*
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* cpu_initclocks:
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*
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* Initialize the clock and get them going.
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*/
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void
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cpu_initclocks(void)
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{
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u_int oldirqstate;
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if (hz < 50 || COUNTS_PER_SEC % hz) {
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printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
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hz = 100;
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}
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tick = 1000000 / hz; /* number of microseconds between interrupts */
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tickfix = 1000000 - (hz * tick);
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if (tickfix) {
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int ftp;
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ftp = min(ffs(tickfix), ffs(hz));
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tickfix >>= (ftp - 1);
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tickfixinterval = hz >> (ftp - 1);
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}
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/*
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* We only have one timer available; stathz and profhz are
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* always left as 0 (the upper-layer clock code deals with
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* this situation).
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*/
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if (stathz != 0)
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printf("Cannot get %d Hz statclock\n", stathz);
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stathz = 0;
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if (profhz != 0)
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printf("Cannot get %d Hz profclock\n", profhz);
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profhz = 0;
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/* Report the clock frequency. */
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printf("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
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/* Hook up the clock interrupt handler. */
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clock_ih = iq80310_intr_establish(XINT3_IRQ(XINT3_TIMER), IPL_CLOCK,
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clockhandler, NULL);
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if (clock_ih == NULL)
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panic("cpu_initclocks: unable to register timer interrupt");
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/* Set up the new clock parameters. */
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oldirqstate = disable_interrupts(I32_bit);
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timer_disable(TIMER_ENABLE_EN);
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counts_per_hz = COUNTS_PER_SEC / hz;
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timer_write(counts_per_hz);
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timer_enable(TIMER_ENABLE_INTEN);
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timer_enable(TIMER_ENABLE_EN);
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restore_interrupts(oldirqstate);
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}
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/*
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* setstatclockrate:
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*
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* Set the rate of the statistics clock.
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*
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* We assume that hz is either stathz or profhz, and that neither
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* will change after being set by cpu_initclocks(). We could
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* recalculate the intervals here, but that would be a pain.
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*/
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void
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setstatclockrate(int hz)
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{
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/*
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* Nothing to do, here; we can't change the statclock
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* rate on the IQ80310.
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*/
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}
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/*
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* microtime:
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*
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* Fill in the specified timeval struct with the current time
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* accurate to the microsecond.
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*/
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void
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microtime(struct timeval *tvp)
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{
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static struct timeval lasttv;
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u_int oldirqstate;
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uint32_t counts;
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oldirqstate = disable_interrupts(I32_bit);
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counts = timer_read();
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/* Fill in the timeval struct. */
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*tvp = time;
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tvp->tv_usec += (counts / COUNTS_PER_USEC);
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/* Make sure microseconds doesn't overflow. */
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while (tvp->tv_usec >= 1000000) {
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tvp->tv_usec -= 1000000;
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tvp->tv_sec++;
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}
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/* Make sure the time has advanced. */
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if (tvp->tv_sec == lasttv.tv_sec &&
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tvp->tv_usec <= lasttv.tv_usec) {
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tvp->tv_usec = lasttv.tv_usec + 1;
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if (tvp->tv_usec >= 1000000) {
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tvp->tv_usec -= 1000000;
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tvp->tv_sec++;
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}
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}
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lasttv = *tvp;
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restore_interrupts(oldirqstate);
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}
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/*
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* delay:
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*
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* Delay for at least N microseconds.
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*/
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void
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delay(u_int n)
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{
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uint32_t cur, last, delta, usecs;
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/*
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* This works by polling the timer and counting the
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* number of microseconds that go by.
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*/
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last = timer_read();
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delta = usecs = 0;
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while (n > usecs) {
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cur = timer_read();
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/* Check to see if the timer has wrapped around. */
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if (cur < last)
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delta += ((counts_per_hz - last) + cur);
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else
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delta += (cur - last);
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last = cur;
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if (delta >= COUNTS_PER_USEC) {
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usecs += delta / COUNTS_PER_USEC;
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delta %= COUNTS_PER_USEC;
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}
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}
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}
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/*
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* inittodr:
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*
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* Initialize time from the time-of-day register.
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*/
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void
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inittodr(time_t base)
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{
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time.tv_sec = base;
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time.tv_usec = 0;
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}
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/*
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* resettodr:
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*
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* Reset the time-of-day register with the current time.
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*/
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void
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resettodr(void)
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{
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}
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/*
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* clockhandler:
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*
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* Handle the hardclock interrupt.
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*/
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int
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clockhandler(void *arg)
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{
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struct clockframe *frame = arg;
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timer_disable(TIMER_ENABLE_INTEN);
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timer_enable(TIMER_ENABLE_INTEN);
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hardclock(frame);
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/*
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* Don't run the snake on IOP310-based systems that
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* don't have the 7-segment display.
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*/
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#if !defined(IOP310_TEAMASA_NPWR)
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{
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static int snakefreq;
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if ((snakefreq++ & 15) == 0)
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iq80310_7seg_snake();
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}
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#endif
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return (1);
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}
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