dsl 27e029a426 Since we always run with CR0.NE set (internal fpu using vector 0x10)
npxintr() is only generated when a process executes an FP instruction
and the TS set interrupt takes precedence - so we know the current lwp
owns the fp registers.
It is also then impossible to get a splurious error while saving
the registers.
Ths lets the npxintr() code be simplified somewhat.
XXX: I'm not at all sure it really DTRT if the process actually wished
to fixup anything in the signal handler (or even if the signal is masked).
2014-02-03 23:00:32 +00:00
2014-01-26 22:38:20 +00:00
2014-01-30 06:39:16 +00:00
2013-12-25 22:14:52 +00:00
2014-01-27 21:37:17 +00:00
2014-02-03 14:15:07 +00:00
2013-12-11 14:59:47 +00:00
2014-01-31 20:44:17 +00:00
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