a079c0eb98
- Handle failure during initalisation more gracefully. - Create a watchdog thread to poke the board and check for status changes. - Make ready for > 64kB transfers.
440 lines
14 KiB
C
440 lines
14 KiB
C
/* $NetBSD: amrreg.h,v 1.2 2003/05/04 16:15:36 ad Exp $ */
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/*-
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* Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1999,2000 Michael Smith
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from FreeBSD: amrreg.h,v 1.2 2000/08/30 07:52:40 msmith Exp
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*/
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#ifndef _PCI_AMRREG_H_
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#define _PCI_AMRREG_H_
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#ifdef AMR_CRASH_ME
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#define AMR_MAX_CMDS 255 /* ident = 0 not allowed */
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#else
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#define AMR_MAX_CMDS 120
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#endif
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#define AMR_MAXLD 40
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#define AMR_MAX_CMDS_PU 63
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#define AMR_MAX_SEGS 26
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#define AMR_MAX_CHANNEL 3
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#define AMR_MAX_TARGET 15
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#define AMR_MAX_LUN 7
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#define AMR_MAX_CDB_LEN 0x0a
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#define AMR_MAX_REQ_SENSE_LEN 0x20
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#define AMR_SECTOR_SIZE 512
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/* Mailbox commands.*/
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#define AMR_CMD_LREAD 0x01
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#define AMR_CMD_LWRITE 0x02
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#define AMR_CMD_PASS 0x03
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#define AMR_CMD_EXT_ENQUIRY 0x04
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#define AMR_CMD_ENQUIRY 0x05
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#define AMR_CMD_FLUSH 0x0a
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#define AMR_CMD_EXT_ENQUIRY2 0x0c
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#define AMR_CMD_GET_MACHINEID 0x36
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#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */
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#define AMR_CMD_CONFIG 0xa1
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#define AMR_CONFIG_PRODUCT_INFO 0x0e
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#define AMR_CONFIG_ENQ3 0x0f
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#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01
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#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02
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#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03
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/* Command completion status. */
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#define AMR_STATUS_SUCCESS 0x00
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#define AMR_STATUS_ABORTED 0x02
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#define AMR_STATUS_FAILED 0x80
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/* Physical/logical drive states. */
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#define AMR_DRV_CURSTATE(x) ((x) & 0x0f)
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#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f)
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#define AMR_DRV_OFFLINE 0x00
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#define AMR_DRV_DEGRADED 0x01
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#define AMR_DRV_OPTIMAL 0x02
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#define AMR_DRV_ONLINE 0x03
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#define AMR_DRV_FAILED 0x04
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#define AMR_DRV_REBUILD 0x05
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#define AMR_DRV_HOTSPARE 0x06
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/* Logical drive properties. */
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#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */
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#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */
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#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */
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#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */
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/* Battery status. */
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#define AMR_BATT_MODULE_MISSING 0x01
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#define AMR_BATT_LOW_VOLTAGE 0x02
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#define AMR_BATT_TEMP_HIGH 0x04
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#define AMR_BATT_PACK_MISSING 0x08
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#define AMR_BATT_CHARGE_MASK 0x30
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#define AMR_BATT_CHARGE_DONE 0x00
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#define AMR_BATT_CHARGE_INPROG 0x10
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#define AMR_BATT_CHARGE_FAIL 0x20
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#define AMR_BATT_CYCLES_EXCEEDED 0x40
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/*
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* 8LD firmware interface.
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*/
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/* Array constraints. */
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#define AMR_8LD_MAXDRIVES 8
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#define AMR_8LD_MAXCHAN 5
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#define AMR_8LD_MAXTARG 15
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#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
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/* Adapter information. */
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struct amr_adapter_info {
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u_int8_t aa_maxio;
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u_int8_t aa_rebuild_rate;
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u_int8_t aa_maxtargchan;
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u_int8_t aa_channels;
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u_int8_t aa_firmware[4];
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u_int16_t aa_flashage;
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u_int8_t aa_chipsetvalue;
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u_int8_t aa_memorysize;
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u_int8_t aa_cacheflush;
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u_int8_t aa_bios[4];
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u_int8_t aa_boardtype;
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u_int8_t aa_scsisensealert;
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u_int8_t aa_writeconfigcount;
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u_int8_t aa_driveinsertioncount;
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u_int8_t aa_inserteddrive;
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u_int8_t aa_batterystatus;
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u_int8_t aa_res1;
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} __attribute__ ((__packed__));
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/* Logical drive information. */
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struct amr_logdrive_info {
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u_int8_t al_numdrives;
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u_int8_t al_res1[3];
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u_int32_t al_size[AMR_8LD_MAXDRIVES];
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u_int8_t al_properties[AMR_8LD_MAXDRIVES];
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u_int8_t al_state[AMR_8LD_MAXDRIVES];
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} __attribute__ ((__packed__));
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/* Physical drive information. */
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struct amr_physdrive_info {
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/* Low nybble is current state, high nybble is previous state. */
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u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES];
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u_int8_t ap_predictivefailure;
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} __attribute__ ((__packed__));
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/*
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* Enquiry response structure for AMR_CMD_ENQUIRY (e), AMR_CMD_EXT_ENQUIRY (x)
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* and AMR_CMD_EXT_ENQUIRY2 (2).
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*/
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struct amr_enquiry {
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struct amr_adapter_info ae_adapter; /* e x 2 */
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struct amr_logdrive_info ae_ldrv; /* e x 2 */
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struct amr_physdrive_info ae_pdrv; /* e x 2 */
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u_int8_t ae_formatting[AMR_8LD_MAXDRIVES]; /* x 2 */
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u_int8_t res1[AMR_8LD_MAXDRIVES]; /* x 2 */
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u_int32_t ae_extlen; /* 2 */
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u_int16_t ae_subsystem; /* 2 */
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u_int16_t ae_subvendor; /* 2 */
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u_int32_t ae_signature; /* 2 */
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#define AMR_SIG_431 0xfffe0001
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#define AMR_SIG_438 0xfffd0002
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#define AMR_SIG_762 0xfffc0003
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#define AMR_SIG_T5 0xfffb0004
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#define AMR_SIG_466 0xfffa0005
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#define AMR_SIG_467 0xfff90006
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#define AMR_SIG_T7 0xfff80007
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#define AMR_SIG_490 0xfff70008
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u_int8_t res2[844]; /* 2 */
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} __attribute__ ((__packed__));
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/*
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* 40LD firmware interface.
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*/
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/* Array constraints. */
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#define AMR_40LD_MAXDRIVES 40
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#define AMR_40LD_MAXCHAN 16
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#define AMR_40LD_MAXTARG 16
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#define AMR_40LD_MAXPHYSDRIVES 256
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/* Product information structure. */
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struct amr_prodinfo {
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u_int32_t ap_size; /* current size in bytes (not including resvd) */
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u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum
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* logical drives, 0x20 maximum stripes and 0x08
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* maximum spans */
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u_int8_t ap_firmware[16]; /* printable identifiers */
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u_int8_t ap_bios[16];
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u_int8_t ap_product[80];
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u_int8_t ap_maxio; /* maximum number of concurrent commands supported */
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u_int8_t ap_nschan; /* number of SCSI channels present */
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u_int8_t ap_fcloops; /* number of fibre loops present */
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u_int8_t ap_memtype; /* memory type */
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u_int32_t ap_signature;
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u_int16_t ap_memsize; /* onboard memory in MB */
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u_int16_t ap_subsystem; /* subsystem identifier */
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u_int16_t ap_subvendor; /* subsystem vendor ID */
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u_int8_t ap_numnotifyctr; /* number of notify counters */
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} __attribute__ ((__packed__));
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/* Notify structure. */
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struct amr_notify {
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u_int32_t an_globalcounter; /* change counter */
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u_int8_t an_paramcounter; /* parameter change counter */
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u_int8_t an_paramid;
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#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */
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#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */
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#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */
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#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */
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#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */
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u_int16_t an_paramval;
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u_int8_t an_writeconfigcounter; /* write config occurred */
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u_int8_t res1[3];
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u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */
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u_int8_t an_ldrvopid;
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u_int8_t an_ldrvopcmd;
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#define AMR_LDRVOP_CHECK 0x01
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#define AMR_LDRVOP_INIT 0x02
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#define AMR_LDRVOP_REBUILD 0x03
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u_int8_t an_ldrvopstatus;
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#define AMR_LDRVOP_SUCCESS 0x00
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#define AMR_LDRVOP_FAILED 0x01
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#define AMR_LDRVOP_ABORTED 0x02
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#define AMR_LDRVOP_CORRECTED 0x03
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#define AMR_LDRVOP_STARTED 0x04
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u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */
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u_int8_t an_ldrvstateid;
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u_int8_t an_ldrvstatenew;
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u_int8_t an_ldrvstateold;
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u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */
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u_int8_t an_pdrvstateid;
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u_int8_t an_pdrvstatenew;
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u_int8_t an_pdrvstateold;
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u_int8_t an_pdrvfmtcounter;
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u_int8_t an_pdrvfmtid;
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u_int8_t an_pdrvfmtval;
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#define AMR_FORMAT_START 0x01
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#define AMR_FORMAT_COMPLETE 0x02
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u_int8_t res2;
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u_int8_t an_targxfercounter; /* scsi xfer rate change */
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u_int8_t an_targxferid;
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u_int8_t an_targxferval;
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u_int8_t res3;
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u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */
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u_int8_t an_fcloopidpdrvid;
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u_int8_t an_fcloopid0;
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u_int8_t an_fcloopid1;
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u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */
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u_int8_t an_fcloopstate0;
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u_int8_t an_fcloopstate1;
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u_int8_t res4;
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} __attribute__ ((__packed__));
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/* Enquiry3 structure. */
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struct amr_enquiry3 {
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u_int32_t ae_datasize; /* valid data size in this structure */
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union { /* event notify structure */
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struct amr_notify n;
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u_int8_t pad[0x80];
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} ae_notify;
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u_int8_t ae_rebuildrate; /* current rebuild rate in % */
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u_int8_t ae_cacheflush; /* flush interval in seconds */
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u_int8_t ae_sensealert;
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u_int8_t ae_driveinsertcount; /* count of inserted drives */
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u_int8_t ae_batterystatus;
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u_int8_t ae_numldrives;
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u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */
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u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */
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u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */
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u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */
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u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */
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u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES];
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u_int8_t ae_targxfer[80]; /* physical drive transfer rates */
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u_int8_t res1[263]; /* pad to 1024 bytes */
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} __attribute__ ((__packed__));
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/*
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* Mailbox and command structures.
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*/
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struct amr_mailbox_cmd {
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int16_t mb_blkcount;
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u_int32_t mb_lba;
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res1;
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u_int8_t mb_busy;
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} __attribute__ ((__packed__));
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struct amr_mailbox_resp {
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u_int8_t mb_nstatus;
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u_int8_t mb_status;
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u_int8_t mb_completed[46];
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} __attribute__ ((__packed__));
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struct amr_mailbox {
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u_int32_t mb_res1[3];
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u_int32_t mb_segment;
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struct amr_mailbox_cmd mb_cmd;
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struct amr_mailbox_resp mb_resp;
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res2[62]; /* Pad to 128+16 bytes. */
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} __attribute__ ((__packed__));
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struct amr_mailbox_ioctl {
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int8_t mb_channel;
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u_int8_t mb_param;
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u_int8_t mb_pad[4];
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res1;
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u_int8_t mb_busy;
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u_int8_t mb_nstatus;
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u_int8_t mb_completed[46];
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res4[16];
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} __attribute__ ((__packed__));
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struct amr_sgentry {
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u_int32_t sge_addr;
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u_int32_t sge_count;
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} __attribute__ ((__packed__));
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struct amr_passthrough {
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u_int8_t ap_timeout:3;
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u_int8_t ap_ars:1;
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u_int8_t ap_dummy:3;
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u_int8_t ap_islogical:1;
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u_int8_t ap_logical_drive_no;
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u_int8_t ap_channel;
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u_int8_t ap_scsi_id;
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u_int8_t ap_queue_tag;
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u_int8_t ap_queue_action;
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u_int8_t ap_cdb[AMR_MAX_CDB_LEN];
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u_int8_t ap_cdb_length;
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u_int8_t ap_request_sense_length;
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u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
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u_int8_t ap_no_sg_elements;
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u_int8_t ap_scsi_status;
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u_int32_t ap_data_transfer_address;
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u_int32_t ap_data_transfer_length;
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} __attribute__ ((__packed__));
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/*
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* "Quartz" i960 PCI bridge interface.
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*/
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#define AMR_QUARTZ_SIG_REG 0xa0
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#define AMR_QUARTZ_SIG0 0xcccc
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#define AMR_QUARTZ_SIG1 0x3344
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/* Doorbell registers. */
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#define AMR_QREG_IDB 0x20
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#define AMR_QREG_ODB 0x2c
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#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */
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#define AMR_QIDB_ACK 0x00000002 /* mailbox done */
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#define AMR_QODB_READY 0x10001234 /* work ready to be processed */
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/*
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* Old-style ("standard") ASIC bridge interface.
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*/
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/* I/O registers. */
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#define AMR_SREG_CMD 0x10 /* Command/ack register (w) */
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#define AMR_SREG_MBOX_BUSY 0x10 /* Mailbox status (r) */
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#define AMR_SREG_TOGL 0x11 /* Interrupt enable */
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#define AMR_SREG_MBOX 0x14 /* Mailbox physical address */
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#define AMR_SREG_MBOX_ENABLE 0x18 /* Atomic mailbox address enable */
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#define AMR_SREG_INTR 0x1a /* Interrupt status */
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/* I/O magic numbers. */
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#define AMR_SCMD_POST 0x10 /* in SCMD to initiate action on mailbox */
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#define AMR_SCMD_ACKINTR 0x08 /* in SCMD to ack mailbox retrieved */
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#define AMR_STOGL_ENABLE 0xc0 /* in STOGL */
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#define AMR_SINTR_VALID 0x40 /* in SINTR */
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#define AMR_SMBOX_BUSY_FLAG 0x10 /* in SMBOX_BUSY */
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#define AMR_SMBOX_ENABLE_ADDR 0x00 /* in SMBOX_ENABLE */
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#endif /* !_PCI_AMRREG_H_ */
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