de1ba9c829
instead of ldstub, but since we aren't doing n-way locking it makes little difference. N.B. Need to decide what to do with sparc64/sparc64/asm.h which has name conflicts with sparc64/include/asm.h. So far most of sparc64/sparc64/asm.h has been moved to ctlreg.h.
198 lines
7.0 KiB
C
198 lines
7.0 KiB
C
/* $NetBSD: asm.h,v 1.5 1999/05/30 18:57:27 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)asm.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* GCC __asm constructs for doing assembly stuff.
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*/
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/*
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* ``Routines'' to load and store from/to alternate address space.
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* The location can be a variable, the asi value (address space indicator)
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* must be a constant.
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*
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* N.B.: You can put as many special functions here as you like, since
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* they cost no kernel space or time if they are not used.
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*
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* These were static inline functions, but gcc screws up the constraints
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* on the address space identifiers (the "n"umeric value part) because
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* it inlines too late, so we have to use the funny valued-macro syntax.
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*/
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/* load byte from alternate address space */
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#define lduba(loc, asi) ({ \
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register int _lduba_v; \
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__asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \
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"r" ((long long)(loc)), "r" (asi)); \
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_lduba_v; \
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})
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/* load half-word from alternate address space */
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#define lduha(loc, asi) ({ \
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register int _lduha_v; \
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__asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \
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"r" ((long long)(loc)), "r" (asi)); \
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_lduha_v; \
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})
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/* load int from alternate address space */
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#define lda(loc, asi) ({ \
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register int _lda_v; \
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__asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \
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"r" ((int)(loc)), "r" (asi)); \
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_lda_v; \
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})
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#define ldswa(loc, asi) ({ \
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register int _lda_v; \
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__asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \
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"r" ((int)(loc)), "r" (asi)); \
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_lda_v; \
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})
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/* store byte to alternate address space */
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#define stba(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; membar #Sync" : : \
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"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
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})
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/* store half-word to alternate address space */
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#define stha(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; membar #Sync" : : \
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"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
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})
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/* store int to alternate address space */
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#define sta(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi; membar #Sync" : : \
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"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
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})
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/* load 64-bit int from alternate address space */
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#define ldda(loc, asi) ({ \
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register long long _lda_v; \
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__asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \
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"r" ((int)(loc)), "r" (asi)); \
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_lda_v; \
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})
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/* store 64-bit int to alternate address space */
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#define stda(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi; membar #Sync" : : \
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"r" ((long long)(value)), "r" ((int)(loc)), "r" (asi)); \
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})
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#ifdef __arch64__
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/* native load 64-bit int from alternate address space w/64-bit compiler*/
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#define ldxa(loc, asi) ({ \
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register long _lda_v; \
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__asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \
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"r" ((long)(loc)), "r" (asi)); \
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_lda_v; \
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})
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#else
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/* native load 64-bit int from alternate address space w/32-bit compiler*/
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#define ldxa(loc, asi) ({ \
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volatile register long _ldxa_tmp = 0; \
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volatile int64_t _ldxa_v; \
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volatile int64_t *_ldxa_a = &_ldxa_v; \
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__asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%1; stx %1,[%3]; membar #Sync" : "=r" (_ldxa_tmp) : \
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"r" ((long)(loc)), "r" (asi), "r" ((long)(_ldxa_a))); \
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_ldxa_v; \
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})
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#endif
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#ifdef __arch64__
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/* native store 64-bit int to alternate address space w/64-bit compiler*/
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#define stxa(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi; membar #Sync" : : \
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"r" ((long)(value)), "r" ((long)(loc)), "r" (asi)); \
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})
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#else
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/* native store 64-bit int to alternate address space w/32-bit compiler*/
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#define stxa(loc, asi, value) ({ \
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int64_t _stxa_v; \
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int64_t *_stxa_a = &_stxa_v; \
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_stxa_v = value; \
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__asm __volatile("wr %2,%%g0,%%asi; ldx [%0],%3; stxa %3,[%1]%%asi; membar #Sync" : : \
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"r" ((long)(_stxa_a)), "r" ((long)(loc)), "r" (asi), "r" ((long)(_stxa_v))); \
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})
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#endif
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/* flush address from data cache */
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#define flush(loc) ({ \
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__asm __volatile("flush %0" : : \
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"r" ((long)(loc))); \
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})
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#define membar_sync() __asm __volatile("membar #Sync" : :)
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#ifdef __arch64__
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/* read 64-bit %tick register */
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#define tick() ({ \
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register long _tick_tmp; \
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__asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \
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_tick_tmp; \
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})
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#else
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/* native load 64-bit int from alternate address space w/32-bit compiler*/
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#define tick() ({ \
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volatile register long _tick_tmp = 0; \
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volatile int64_t _tick_v; \
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volatile int64_t *_tick_a = &_tick_v; \
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__asm __volatile("rdpr %%tick, %0; stx %0,[%1]; membar #StoreLoad" : "=r" (_tick_tmp) : \
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"r" ((long)(_tick_a))); \
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_tick_v; \
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})
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#endif
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/* atomic load/store of a byte in memory */
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#define ldstub(loc) ({ \
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int _v; \
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__asm __volatile("ldstub [%1],%0" : "=r" (_v) : "r" (loc) : "memory"); \
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_v; \
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})
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