137 lines
5.5 KiB
C
137 lines
5.5 KiB
C
/* $NetBSD: imx31_intr.h,v 1.3 2008/04/28 20:23:14 martin Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX31_INTR_H_
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#define _ARM_IMX_IMX31_INTR_H_
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#define IRQ__RSVD0 0
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#define IRQ__RSVD1 1
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#define IRQ__RSVD2 2
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#define IRQ_I2C3 3 /* I2C 3 */
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#define IRQ_I2C2 4 /* I2C 2 */
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#define IRQ_MPEG4_ENC 5 /* MPEG-4 Encoder */
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#define IRQ_RTIC 6 /* RTIC */
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#define IRQ_FIR 7 /* Fast Infrared */
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#define IRQ_MMSD_HC2 8 /* MultiMedia/Secure Data Host Controller 2 */
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#define IRQ_MMSD_HC1 9 /* MultiMedia/Secure Data Host Controller 1 */
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#define IRQ_I2C1 10 /* i2c 1 */
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#define IRQ_SSI2 11 /* Synchronous Serial Interface 1 */
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#define IRQ_SSI1 12 /* Synchronous Serial Interface 2 */
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#define IRQ_CSPI2 13 /* Configurable Serial Peripheral Intf 2 */
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#define IRQ_CSPI1 14 /* Configurable Serial Peripheral Intf 1 */
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#define IRQ_ATA 15 /* Hard Drive (ATA) Controller */
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#define IRQ_MBX_RS 16 /* Graphics Accelerator */
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#define IRQ_CSPI3 17 /* Configurable Serial Peripheral Intf 3 */
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#define IRQ_UART3 18 /* UART3 (rx,tx,mint) */
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#define IRQ_I2C_ID 19 /* IC identification */
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#define IRQ_SIM1 20 /* Subscriber Identification Module */
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#define IRQ_SIM2 21 /* Subscriber Identification Module */
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#define IRQ_RNGA 22 /* Random Number Generator Accelerator */
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#define IRQ_EVTMON 23 /* event monitor + pmu */
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#define IRQ_KPP 24 /* Keyboard Port Port */
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#define IRQ_RTC 25 /* Real Time Clock */
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#define IRQ_PWM 26 /* Pulse Width Modulator */
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#define IRQ_EPIT2 27 /* Enhanced Periodic Timer 2 */
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#define IRQ_EPIT1 28 /* Enhanced Periodic Timer 1 */
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#define IRQ_GPT 29 /* General Purpose Timer */
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#define IRQ_PWRFAIL 30 /* Power Fail */
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#define IRQ_CCM_DVFS 31 /* Configurable Serial Peripheral Intf 3 */
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#define IRQ_UART2 32 /* UART2 (rx,tx,mint) */
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#define IRQ_NANDFC 33 /* NAND Flash Controller */
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#define IRQ_SDMA 34 /* Smart Direct Memory Access */
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#define IRQ_USB_H1 35 /* USB Host 1 */
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#define IRQ_USB_H2 36 /* USB Host 2 */
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#define IRQ_USB_OTG 37 /* USB OTG */
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#define IRQ__RSVD38 38 /* */
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#define IRQ_MS_HC1 39 /* Memory Stick Host Controller 1 */
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#define IRQ_MS_HC2 40 /* Memory Stick Host Controller 2 */
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#define IRQ_IPU_ERR 41 /* */
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#define IRQ_IPU 42 /* */
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#define IRQ__RSVD43 43 /* */
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#define IRQ__RSVD44 44 /* */
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#define IRQ_UART1 45 /* UART1 (rx,tx,mint) */
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#define IRQ_UART4 46 /* UART4 (rx,tx,mint) */
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#define IRQ_UART5 47 /* UART5 (rx,tx,mint) */
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#define IRQ_ECT 48 /* */
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#define IRQ_SCC_SCM 49 /* SCM interrupt */
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#define IRQ_SCC_SMN 50 /* SMN interrupt */
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#define IRQ_GPIO2 51 /* General Purpose I/O 2 */
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#define IRQ_GPIO1 52 /* General Purpose I/O 1 */
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#define IRQ_CCM 53 /* Clock Controller */
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#define IRQ_PCMCIA 54 /* PCMCIA Controller 3 */
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#define IRQ_WDOG 55 /* Watchdog Timer */
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#define IRQ_GPIO3 56 /* General Purpose I/O 3 */
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#define IRQ__RSVD57 57
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#define IRQ_EXT_PWRMGT 58 /* External (power managerment) */
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#define IRQ_EXT_TEMP 59 /* External (Temperture) */
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#define IRQ_EXT_SENS2 60 /* External (sensor) */
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#define IRQ_EXT_SENS1 61 /* External (sensor) */
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#define IRQ_EXT_WDOG 62 /* External (WDOG) */
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#define IRQ_EXT_TV 63 /* External (TV) 3 */
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#ifdef _LOCORE
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#define ARM_IRQ_HANDLER _C_LABEL(imx31_irq_handler)
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#else
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#define AVIC_INTR_SOURCE_NAMES \
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{ "reserved 0", "reserved 1", "reserved 2", "i2c #3", \
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"i2c #2", "mpeg4 enc", "rtic", "fir", \
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"mm/sd hc #2", "mm/sd hc #1", "i2c #1", "ssi #2", \
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"ssi #1", "cspi #2", "cspi #1", "ata", \
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"mbx rs", "cspi #3", "uart #3", "i2c id", \
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"sim #1", "sim #2", "rnga", "evtmon", \
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"kpp", "rtc", "pwm", "epit #2", \
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"epit #1", "gpt", "pwrfail", "ccm dvfs", \
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"uart #2", "nandfc", "sdma", "usb hc #1", \
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"usb hc #2", "usb otg", "reserved 38", "ms hc #1", \
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"ms hc#2", "ipu err", "ipu", "reserved 43", \
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"reserved 44", "uart #1", "uart #4", "uart #5", \
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"ect", "scc scm", "scc smn", "gpio #2", \
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"gpio #1", "ccm", "pcmcia", "wdog", \
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"gpio #3", "reserved 57", "ext pwrmgt", "ext temp", \
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"ext sens #2", "ext sens #1", "ext wdog", "ext tv", }
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#define PIC_MAXMAXSOURCES (64+3*32+128)
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#include <arm/pic/picvar.h>
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int _splraise(int);
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int _spllower(int);
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void splx(int);
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const char *
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intr_typename(int);
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void imx31_irq_handler(void *);
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#endif /* !_LOCORE */
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#endif /* _ARM_IMX_IMX31_INTR_H_ */
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