451 lines
11 KiB
C
451 lines
11 KiB
C
/* $NetBSD: gemini_pci.c,v 1.8 2010/01/05 13:14:56 mbalmer Exp $ */
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/* adapted from:
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* NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp
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*/
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI configuration support for i80312 Companion I/O chip.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.8 2010/01/05 13:14:56 mbalmer Exp $");
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/pic/picvar.h>
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#include <arm/gemini/gemini_reg.h>
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#include <arm/gemini/gemini_pcivar.h>
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#include <arm/gemini/gemini_obiovar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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#include <machine/pci_machdep.h>
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#include "opt_gemini.h"
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#include "opt_pci.h"
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#include "pci.h"
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void gemini_pci_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int gemini_pci_bus_maxdevs(void *, int);
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pcitag_t gemini_pci_make_tag(void *, int, int, int);
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void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *,
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int *);
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pcireg_t gemini_pci_conf_read(void *, pcitag_t, int);
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void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t);
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int gemini_pci_conf_hook(pci_chipset_tag_t, int, int, int,
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pcireg_t);
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int gemini_pci_intr_map(struct pci_attach_args *,
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pci_intr_handle_t *);
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const char *gemini_pci_intr_string(void *, pci_intr_handle_t);
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const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t);
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void *gemini_pci_intr_establish(void *, pci_intr_handle_t,
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int, int (*)(void *), void *);
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void gemini_pci_intr_disestablish(void *, void *);
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int gemini_pci_intr_handler(void *v);
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#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
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#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
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struct gemini_pci_intrq {
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SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q;
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int (*iq_func)(void *);
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void *iq_arg;
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void *iq_ih;
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};
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static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq =
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SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq);
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static inline int
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gemini_pci_intrq_empty(void)
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{
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return SIMPLEQ_EMPTY(&gemini_pci_intrq);
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}
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static inline void *
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gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg)
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{
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struct gemini_pci_intrq *iqp;
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iqp = malloc(sizeof(*iqp), M_DEVBUF, M_NOWAIT|M_ZERO);
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if (iqp == NULL) {
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printf("gemini_pci_intrq_insert: malloc failed\n");
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return NULL;
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}
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iqp->iq_func = func;
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iqp->iq_arg = arg;
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iqp->iq_ih = ih;
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SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q);
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return (void *)iqp;
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}
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static inline void
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gemini_pci_intrq_remove(void *cookie)
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{
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struct gemini_pci_intrq *iqp;
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SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) {
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if ((void *)iqp == cookie) {
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SIMPLEQ_REMOVE(&gemini_pci_intrq,
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iqp, gemini_pci_intrq, iq_q);
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free(iqp, M_DEVBUF);
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return;
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}
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}
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}
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static inline int
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gemini_pci_intrq_dispatch(void)
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{
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struct gemini_pci_intrq *iqp;
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SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) {
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(*iqp->iq_func)(iqp->iq_arg);
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}
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return 1;
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}
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void
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gemini_pci_init(pci_chipset_tag_t pc, void *cookie)
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{
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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struct obio_softc *sc = cookie;
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struct extent *ioext, *memext;
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#endif
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pc->pc_conf_v = cookie;
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pc->pc_attach_hook = gemini_pci_attach_hook;
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pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs;
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pc->pc_make_tag = gemini_pci_make_tag;
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pc->pc_decompose_tag = gemini_pci_decompose_tag;
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pc->pc_conf_read = gemini_pci_conf_read;
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pc->pc_conf_write = gemini_pci_conf_write;
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pc->pc_intr_v = cookie;
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pc->pc_intr_map = gemini_pci_intr_map;
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pc->pc_intr_string = gemini_pci_intr_string;
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pc->pc_intr_evcnt = gemini_pci_intr_evcnt;
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pc->pc_intr_establish = gemini_pci_intr_establish;
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pc->pc_intr_disestablish = gemini_pci_intr_disestablish;
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pc->pc_conf_hook = gemini_pci_conf_hook;
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/*
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* initialize copy of CFG_CMD
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*/
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sc->sc_pci_chipset.pc_cfg_cmd =
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gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD);
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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/*
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* Configure the PCI bus.
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*
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* XXX We need to revisit this. We only configure the Secondary
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* bus (and its children). The bus configure code needs changes
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* to support how the busses are arranged on this chip. We also
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* need to only configure devices in the private device space on
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* the Secondary bus.
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*/
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aprint_normal("%s: configuring Secondary PCI bus\n",
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device_xname(sc->sc_dev));
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/*
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* XXX PCI IO addr should be inherited ?
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*/
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ioext = extent_create("pciio",
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GEMINI_PCIIO_BASE,
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GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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/*
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* XXX PCI mem addr should be inherited ?
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*/
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memext = extent_create("pcimem",
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GEMINI_PCIMEM_BASE,
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GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
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gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1,
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PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024)))
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| gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024));
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extent_destroy(ioext);
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extent_destroy(memext);
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#endif
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
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{
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}
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int
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gemini_pci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, pcireg_t id)
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{
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int rv;
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rv = PCI_CONF_ALL;
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return rv;
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}
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void
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gemini_pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* Nothing to do. */
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}
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int
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gemini_pci_bus_maxdevs(void *v, int busno)
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{
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return (32);
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}
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pcitag_t
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gemini_pci_make_tag(void *v, int b, int d, int f)
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{
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return ((b << 16) | (d << 11) | (f << 8));
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}
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void
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gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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struct pciconf_state {
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uint32_t ps_addr_val;
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int ps_b, ps_d, ps_f;
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};
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static int
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gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset,
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struct pciconf_state *ps)
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{
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gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
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ps->ps_addr_val =
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PCI_CFG_CMD_ENB
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| PCI_CFG_CMD_BUSn(ps->ps_b)
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| PCI_CFG_CMD_DEVn(ps->ps_d)
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| PCI_CFG_CMD_FUNCn(ps->ps_f)
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| PCI_CFG_CMD_REGn(offset);
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return (0);
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}
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pcireg_t
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gemini_pci_conf_read(void *v, pcitag_t tag, int offset)
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{
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struct obio_softc *sc = v;
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struct pciconf_state ps;
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vaddr_t va;
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pcireg_t rv;
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u_int s;
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if (gemini_pci_conf_setup(sc, tag, offset, &ps))
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return ((pcireg_t) -1);
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PCI_CONF_LOCK(s);
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if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) {
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sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val;
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bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
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GEMINI_PCI_CFG_CMD, ps.ps_addr_val);
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}
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va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh);
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if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) {
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/*
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* XXX Clear the Master Abort
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*/
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#if 1
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printf("conf_read: %d/%d/%d bad address\n",
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ps.ps_b, ps.ps_d, ps.ps_f);
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#endif
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rv = (pcireg_t) -1;
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}
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PCI_CONF_UNLOCK(s);
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return (rv);
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}
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void
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gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
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{
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struct obio_softc *sc = v;
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struct pciconf_state ps;
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u_int s;
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if (gemini_pci_conf_setup(sc, tag, offset, &ps))
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return;
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PCI_CONF_LOCK(s);
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if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) {
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sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val;
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bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
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GEMINI_PCI_CFG_CMD, ps.ps_addr_val);
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}
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bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
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GEMINI_PCI_CFG_DATA, val);
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PCI_CONF_UNLOCK(s);
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}
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int
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gemini_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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int irq;
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irq = 8;
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*ihp = irq;
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return 0;
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}
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const char *
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gemini_pci_intr_string(void *v, pci_intr_handle_t ih)
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{
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const char *name = "pci";
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return (name);
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}
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const struct evcnt *
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gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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return NULL;
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}
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void *
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gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl,
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int (*func)(void *), void *arg)
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{
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pcireg_t r;
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void *ih=NULL;
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int irq;
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void *cookie;
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irq = (int)pci_ih;
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r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
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r |= CFG_REG_CTL2_INTMASK_INT_ABCD;
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gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
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if (gemini_pci_intrq_empty())
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ih = intr_establish(irq, ipl, IST_LEVEL_HIGH,
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gemini_pci_intr_handler, v);
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cookie = gemini_pci_intrq_insert(ih, func, arg);
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if (cookie == NULL) {
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if (gemini_pci_intrq_empty())
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intr_disestablish(ih);
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}
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return cookie;
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}
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void
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gemini_pci_intr_disestablish(void *v, void *cookie)
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{
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pcireg_t r;
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struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie;
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void *ih = iqp->iq_ih;
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gemini_pci_intrq_remove(cookie);
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if (gemini_pci_intrq_empty()) {
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r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
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r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD;
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gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
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intr_disestablish(ih);
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}
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}
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int
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gemini_pci_intr_handler(void *v)
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{
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pcireg_t r;
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int rv;
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/*
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* dispatch PCI device interrupt handlers
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*/
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rv = gemini_pci_intrq_dispatch();
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/*
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* ack Gemini PCI interrupts
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*/
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r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
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gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
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return rv;
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}
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