943 lines
30 KiB
ArmAsm
943 lines
30 KiB
ArmAsm
#
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# $NetBSD: ilsp.s,v 1.2 1996/05/15 19:48:37 is Exp $
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#
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#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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# MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
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# M68000 Hi-Performance Microprocessor Division
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# M68060 Software Package Production Release
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#
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# M68060 Software Package Copyright (C) 1993, 1994, 1995, 1996 Motorola Inc.
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# All rights reserved.
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#
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# THE SOFTWARE is provided on an "AS IS" basis and without warranty.
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# To the maximum extent permitted by applicable law,
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# MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
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# INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
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# FOR A PARTICULAR PURPOSE and any warranty against infringement with
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# regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
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# and any accompanying written materials.
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#
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# To the maximum extent permitted by applicable law,
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# IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
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# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
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# BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
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# ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
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#
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# Motorola assumes no responsibility for the maintenance and support
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# of the SOFTWARE.
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#
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# You are hereby granted a copyright license to use, modify, and distribute the
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# SOFTWARE so long as this entire notice is retained without alteration
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# in any modified and/or redistributed versions, and that such modified
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# versions are clearly identified as such.
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# No licenses are granted by implication, estoppel or otherwise under any
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# patents or trademarks of Motorola, Inc.
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#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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#
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# litop.s:
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# This file is appended to the top of the 060FPLSP package
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# and contains the entry points into the package. The user, in
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# effect, branches to one of the branch table entries located here.
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#
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bra.l _060LSP__idivs64_
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short 0x0000
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bra.l _060LSP__idivu64_
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short 0x0000
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bra.l _060LSP__imuls64_
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short 0x0000
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bra.l _060LSP__imulu64_
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short 0x0000
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bra.l _060LSP__cmp2_Ab_
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short 0x0000
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bra.l _060LSP__cmp2_Aw_
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short 0x0000
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bra.l _060LSP__cmp2_Al_
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short 0x0000
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bra.l _060LSP__cmp2_Db_
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short 0x0000
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bra.l _060LSP__cmp2_Dw_
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short 0x0000
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bra.l _060LSP__cmp2_Dl_
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short 0x0000
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# leave room for future possible aditions.
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align 0x200
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#########################################################################
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# XDEF **************************************************************** #
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# _060LSP__idivu64_(): Emulate 64-bit unsigned div instruction. #
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# _060LSP__idivs64_(): Emulate 64-bit signed div instruction. #
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# #
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# This is the library version which is accessed as a subroutine #
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# and therefore does not work exactly like the 680X0 div{s,u}.l #
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# 64-bit divide instruction. #
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# #
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# XREF **************************************************************** #
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# None. #
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# #
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# INPUT *************************************************************** #
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# 0x4(sp) = divisor #
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# 0x8(sp) = hi(dividend) #
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# 0xc(sp) = lo(dividend) #
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# 0x10(sp) = pointer to location to place quotient/remainder #
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# #
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# OUTPUT ************************************************************** #
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# 0x10(sp) = points to location of remainder/quotient. #
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# remainder is in first longword, quotient is in 2nd. #
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# #
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# ALGORITHM *********************************************************** #
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# If the operands are signed, make them unsigned and save the #
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# sign info for later. Separate out special cases like divide-by-zero #
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# or 32-bit divides if possible. Else, use a special math algorithm #
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# to calculate the result. #
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# Restore sign info if signed instruction. Set the condition #
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# codes before performing the final "rts". If the divisor was equal to #
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# zero, then perform a divide-by-zero using a 16-bit implemented #
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# divide instruction. This way, the operating system can record that #
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# the event occurred even though it may not point to the correct place. #
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# #
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#########################################################################
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set POSNEG, -1
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set NDIVISOR, -2
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set NDIVIDEND, -3
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set DDSECOND, -4
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set DDNORMAL, -8
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set DDQUOTIENT, -12
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set DIV64_CC, -16
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##########
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# divs.l #
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##########
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global _060LSP__idivs64_
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_060LSP__idivs64_:
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# PROLOGUE BEGIN ########################################################
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link.w %a6,&-16
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movm.l &0x3f00,-(%sp) # save d2-d7
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# fmovm.l &0x0,-(%sp) # save no fpregs
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# PROLOGUE END ##########################################################
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mov.w %cc,DIV64_CC(%a6)
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st POSNEG(%a6) # signed operation
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bra.b ldiv64_cont
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##########
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# divu.l #
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##########
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global _060LSP__idivu64_
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_060LSP__idivu64_:
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# PROLOGUE BEGIN ########################################################
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link.w %a6,&-16
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movm.l &0x3f00,-(%sp) # save d2-d7
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# fmovm.l &0x0,-(%sp) # save no fpregs
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# PROLOGUE END ##########################################################
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mov.w %cc,DIV64_CC(%a6)
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sf POSNEG(%a6) # unsigned operation
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ldiv64_cont:
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mov.l 0x8(%a6),%d7 # fetch divisor
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beq.w ldiv64eq0 # divisor is = 0!!!
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mov.l 0xc(%a6), %d5 # get dividend hi
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mov.l 0x10(%a6), %d6 # get dividend lo
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# separate signed and unsigned divide
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tst.b POSNEG(%a6) # signed or unsigned?
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beq.b ldspecialcases # use positive divide
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# save the sign of the divisor
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# make divisor unsigned if it's negative
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tst.l %d7 # chk sign of divisor
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slt NDIVISOR(%a6) # save sign of divisor
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bpl.b ldsgndividend
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neg.l %d7 # complement negative divisor
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# save the sign of the dividend
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# make dividend unsigned if it's negative
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ldsgndividend:
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tst.l %d5 # chk sign of hi(dividend)
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slt NDIVIDEND(%a6) # save sign of dividend
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bpl.b ldspecialcases
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mov.w &0x0, %cc # clear 'X' cc bit
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negx.l %d6 # complement signed dividend
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negx.l %d5
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# extract some special cases:
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# - is (dividend == 0) ?
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# - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
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ldspecialcases:
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tst.l %d5 # is (hi(dividend) == 0)
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bne.b ldnormaldivide # no, so try it the long way
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tst.l %d6 # is (lo(dividend) == 0), too
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beq.w lddone # yes, so (dividend == 0)
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cmp.l %d7,%d6 # is (divisor <= lo(dividend))
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bls.b ld32bitdivide # yes, so use 32 bit divide
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exg %d5,%d6 # q = 0, r = dividend
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bra.w ldivfinish # can't divide, we're done.
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ld32bitdivide:
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tdivu.l %d7, %d5:%d6 # it's only a 32/32 bit div!
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bra.b ldivfinish
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ldnormaldivide:
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# last special case:
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# - is hi(dividend) >= divisor ? if yes, then overflow
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cmp.l %d7,%d5
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bls.b lddovf # answer won't fit in 32 bits
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# perform the divide algorithm:
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bsr.l ldclassical # do int divide
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# separate into signed and unsigned finishes.
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ldivfinish:
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tst.b POSNEG(%a6) # do divs, divu separately
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beq.b lddone # divu has no processing!!!
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# it was a divs.l, so ccode setting is a little more complicated...
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tst.b NDIVIDEND(%a6) # remainder has same sign
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beq.b ldcc # as dividend.
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neg.l %d5 # sgn(rem) = sgn(dividend)
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ldcc:
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mov.b NDIVISOR(%a6), %d0
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eor.b %d0, NDIVIDEND(%a6) # chk if quotient is negative
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beq.b ldqpos # branch to quot positive
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# 0x80000000 is the largest number representable as a 32-bit negative
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# number. the negative of 0x80000000 is 0x80000000.
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cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits?
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bhi.b lddovf
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neg.l %d6 # make (-quot) 2's comp
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bra.b lddone
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ldqpos:
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btst &0x1f, %d6 # will (+quot) fit in 32 bits?
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bne.b lddovf
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lddone:
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# if the register numbers are the same, only the quotient gets saved.
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# so, if we always save the quotient second, we save ourselves a cmp&beq
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andi.w &0x10,DIV64_CC(%a6)
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mov.w DIV64_CC(%a6),%cc
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tst.l %d6 # may set 'N' ccode bit
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# here, the result is in d1 and d0. the current strategy is to save
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# the values at the location pointed to by a0.
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# use movm here to not disturb the condition codes.
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ldexit:
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movm.l &0x0060,([0x14,%a6]) # save result
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# EPILOGUE BEGIN ########################################################
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# fmovm.l (%sp)+,&0x0 # restore no fpregs
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movm.l (%sp)+,&0x00fc # restore d2-d7
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unlk %a6
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# EPILOGUE END ##########################################################
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rts
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# the result should be the unchanged dividend
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lddovf:
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mov.l 0xc(%a6), %d5 # get dividend hi
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mov.l 0x10(%a6), %d6 # get dividend lo
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andi.w &0x1c,DIV64_CC(%a6)
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ori.w &0x02,DIV64_CC(%a6) # set 'V' ccode bit
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mov.w DIV64_CC(%a6),%cc
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bra.b ldexit
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ldiv64eq0:
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mov.l 0xc(%a6),([0x14,%a6])
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mov.l 0x10(%a6),([0x14,%a6],0x4)
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mov.w DIV64_CC(%a6),%cc
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# EPILOGUE BEGIN ########################################################
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# fmovm.l (%sp)+,&0x0 # restore no fpregs
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movm.l (%sp)+,&0x00fc # restore d2-d7
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unlk %a6
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# EPILOGUE END ##########################################################
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divu.w &0x0,%d0 # force a divbyzero exception
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rts
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###########################################################################
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#########################################################################
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# This routine uses the 'classical' Algorithm D from Donald Knuth's #
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# Art of Computer Programming, vol II, Seminumerical Algorithms. #
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# For this implementation b=2**16, and the target is U1U2U3U4/V1V2, #
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# where U,V are words of the quadword dividend and longword divisor, #
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# and U1, V1 are the most significant words. #
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# #
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# The most sig. longword of the 64 bit dividend must be in %d5, least #
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# in %d6. The divisor must be in the variable ddivisor, and the #
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# signed/unsigned flag ddusign must be set (0=unsigned,1=signed). #
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# The quotient is returned in %d6, remainder in %d5, unless the #
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# v (overflow) bit is set in the saved %ccr. If overflow, the dividend #
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# is unchanged. #
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#########################################################################
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ldclassical:
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# if the divisor msw is 0, use simpler algorithm then the full blown
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# one at ddknuth:
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cmpi.l %d7, &0xffff
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bhi.b lddknuth # go use D. Knuth algorithm
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# Since the divisor is only a word (and larger than the mslw of the dividend),
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# a simpler algorithm may be used :
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# In the general case, four quotient words would be created by
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# dividing the divisor word into each dividend word. In this case,
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# the first two quotient words must be zero, or overflow would occur.
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# Since we already checked this case above, we can treat the most significant
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# longword of the dividend as (0) remainder (see Knuth) and merely complete
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# the last two divisions to get a quotient longword and word remainder:
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clr.l %d1
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swap %d5 # same as r*b if previous step rqd
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swap %d6 # get u3 to lsw position
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mov.w %d6, %d5 # rb + u3
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divu.w %d7, %d5
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mov.w %d5, %d1 # first quotient word
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swap %d6 # get u4
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mov.w %d6, %d5 # rb + u4
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divu.w %d7, %d5
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swap %d1
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mov.w %d5, %d1 # 2nd quotient 'digit'
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clr.w %d5
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swap %d5 # now remainder
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mov.l %d1, %d6 # and quotient
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rts
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lddknuth:
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# In this algorithm, the divisor is treated as a 2 digit (word) number
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# which is divided into a 3 digit (word) dividend to get one quotient
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# digit (word). After subtraction, the dividend is shifted and the
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# process repeated. Before beginning, the divisor and quotient are
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# 'normalized' so that the process of estimating the quotient digit
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# will yield verifiably correct results..
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clr.l DDNORMAL(%a6) # count of shifts for normalization
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clr.b DDSECOND(%a6) # clear flag for quotient digits
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clr.l %d1 # %d1 will hold trial quotient
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lddnchk:
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btst &31, %d7 # must we normalize? first word of
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bne.b lddnormalized # divisor (V1) must be >= 65536/2
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addq.l &0x1, DDNORMAL(%a6) # count normalization shifts
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lsl.l &0x1, %d7 # shift the divisor
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lsl.l &0x1, %d6 # shift u4,u3 with overflow to u2
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roxl.l &0x1, %d5 # shift u1,u2
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bra.w lddnchk
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lddnormalized:
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# Now calculate an estimate of the quotient words (msw first, then lsw).
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# The comments use subscripts for the first quotient digit determination.
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mov.l %d7, %d3 # divisor
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mov.l %d5, %d2 # dividend mslw
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swap %d2
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swap %d3
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cmp.w %d2, %d3 # V1 = U1 ?
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bne.b lddqcalc1
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mov.w &0xffff, %d1 # use max trial quotient word
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bra.b lddadj0
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lddqcalc1:
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mov.l %d5, %d1
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divu.w %d3, %d1 # use quotient of mslw/msw
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andi.l &0x0000ffff, %d1 # zero any remainder
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lddadj0:
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# now test the trial quotient and adjust. This step plus the
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# normalization assures (according to Knuth) that the trial
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# quotient will be at worst 1 too large.
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mov.l %d6, -(%sp)
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clr.w %d6 # word u3 left
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swap %d6 # in lsw position
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lddadj1: mov.l %d7, %d3
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mov.l %d1, %d2
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mulu.w %d7, %d2 # V2q
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swap %d3
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mulu.w %d1, %d3 # V1q
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mov.l %d5, %d4 # U1U2
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sub.l %d3, %d4 # U1U2 - V1q
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swap %d4
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mov.w %d4,%d0
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mov.w %d6,%d4 # insert lower word (U3)
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tst.w %d0 # is upper word set?
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bne.w lddadjd1
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# add.l %d6, %d4 # (U1U2 - V1q) + U3
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cmp.l %d2, %d4
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bls.b lddadjd1 # is V2q > (U1U2-V1q) + U3 ?
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subq.l &0x1, %d1 # yes, decrement and recheck
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bra.b lddadj1
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lddadjd1:
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# now test the word by multiplying it by the divisor (V1V2) and comparing
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# the 3 digit (word) result with the current dividend words
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mov.l %d5, -(%sp) # save %d5 (%d6 already saved)
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mov.l %d1, %d6
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swap %d6 # shift answer to ms 3 words
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mov.l %d7, %d5
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bsr.l ldmm2
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mov.l %d5, %d2 # now %d2,%d3 are trial*divisor
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mov.l %d6, %d3
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mov.l (%sp)+, %d5 # restore dividend
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mov.l (%sp)+, %d6
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sub.l %d3, %d6
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subx.l %d2, %d5 # subtract double precision
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bcc ldd2nd # no carry, do next quotient digit
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subq.l &0x1, %d1 # q is one too large
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# need to add back divisor longword to current ms 3 digits of dividend
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# - according to Knuth, this is done only 2 out of 65536 times for random
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# divisor, dividend selection.
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clr.l %d2
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mov.l %d7, %d3
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swap %d3
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clr.w %d3 # %d3 now ls word of divisor
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add.l %d3, %d6 # aligned with 3rd word of dividend
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addx.l %d2, %d5
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mov.l %d7, %d3
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clr.w %d3 # %d3 now ms word of divisor
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swap %d3 # aligned with 2nd word of dividend
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add.l %d3, %d5
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ldd2nd:
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tst.b DDSECOND(%a6) # both q words done?
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bne.b lddremain
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# first quotient digit now correct. store digit and shift the
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# (subtracted) dividend
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mov.w %d1, DDQUOTIENT(%a6)
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clr.l %d1
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swap %d5
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swap %d6
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mov.w %d6, %d5
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clr.w %d6
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st DDSECOND(%a6) # second digit
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bra.w lddnormalized
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lddremain:
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# add 2nd word to quotient, get the remainder.
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mov.w %d1, DDQUOTIENT+2(%a6)
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# shift down one word/digit to renormalize remainder.
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mov.w %d5, %d6
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swap %d6
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swap %d5
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mov.l DDNORMAL(%a6), %d7 # get norm shift count
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beq.b lddrn
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subq.l &0x1, %d7 # set for loop count
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lddnlp:
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lsr.l &0x1, %d5 # shift into %d6
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roxr.l &0x1, %d6
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dbf %d7, lddnlp
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lddrn:
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mov.l %d6, %d5 # remainder
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mov.l DDQUOTIENT(%a6), %d6 # quotient
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rts
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ldmm2:
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# factors for the 32X32->64 multiplication are in %d5 and %d6.
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# returns 64 bit result in %d5 (hi) %d6(lo).
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# destroys %d2,%d3,%d4.
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|
|
|
# multiply hi,lo words of each factor to get 4 intermediate products
|
|
mov.l %d6, %d2
|
|
mov.l %d6, %d3
|
|
mov.l %d5, %d4
|
|
swap %d3
|
|
swap %d4
|
|
mulu.w %d5, %d6 # %d6 <- lsw*lsw
|
|
mulu.w %d3, %d5 # %d5 <- msw-dest*lsw-source
|
|
mulu.w %d4, %d2 # %d2 <- msw-source*lsw-dest
|
|
mulu.w %d4, %d3 # %d3 <- msw*msw
|
|
# now use swap and addx to consolidate to two longwords
|
|
clr.l %d4
|
|
swap %d6
|
|
add.w %d5, %d6 # add msw of l*l to lsw of m*l product
|
|
addx.w %d4, %d3 # add any carry to m*m product
|
|
add.w %d2, %d6 # add in lsw of other m*l product
|
|
addx.w %d4, %d3 # add any carry to m*m product
|
|
swap %d6 # %d6 is low 32 bits of final product
|
|
clr.w %d5
|
|
clr.w %d2 # lsw of two mixed products used,
|
|
swap %d5 # now use msws of longwords
|
|
swap %d2
|
|
add.l %d2, %d5
|
|
add.l %d3, %d5 # %d5 now ms 32 bits of final product
|
|
rts
|
|
|
|
#########################################################################
|
|
# XDEF **************************************************************** #
|
|
# _060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction #
|
|
# _060LSP__imuls64_(): Emulate 64-bit signed mul instruction. #
|
|
# #
|
|
# This is the library version which is accessed as a subroutine #
|
|
# and therefore does not work exactly like the 680X0 mul{s,u}.l #
|
|
# 64-bit multiply instruction. #
|
|
# #
|
|
# XREF **************************************************************** #
|
|
# None #
|
|
# #
|
|
# INPUT *************************************************************** #
|
|
# 0x4(sp) = multiplier #
|
|
# 0x8(sp) = multiplicand #
|
|
# 0xc(sp) = pointer to location to place 64-bit result #
|
|
# #
|
|
# OUTPUT ************************************************************** #
|
|
# 0xc(sp) = points to location of 64-bit result #
|
|
# #
|
|
# ALGORITHM *********************************************************** #
|
|
# Perform the multiply in pieces using 16x16->32 unsigned #
|
|
# multiplies and "add" instructions. #
|
|
# Set the condition codes as appropriate before performing an #
|
|
# "rts". #
|
|
# #
|
|
#########################################################################
|
|
|
|
set MUL64_CC, -4
|
|
|
|
global _060LSP__imulu64_
|
|
_060LSP__imulu64_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,MUL64_CC(%a6) # save incomming ccodes
|
|
|
|
mov.l 0x8(%a6),%d0 # store multiplier in d0
|
|
beq.w mulu64_zero # handle zero separately
|
|
|
|
mov.l 0xc(%a6),%d1 # get multiplicand in d1
|
|
beq.w mulu64_zero # handle zero separately
|
|
|
|
#########################################################################
|
|
# 63 32 0 #
|
|
# ---------------------------- #
|
|
# | hi(mplier) * hi(mplicand)| #
|
|
# ---------------------------- #
|
|
# ----------------------------- #
|
|
# | hi(mplier) * lo(mplicand) | #
|
|
# ----------------------------- #
|
|
# ----------------------------- #
|
|
# | lo(mplier) * hi(mplicand) | #
|
|
# ----------------------------- #
|
|
# | ----------------------------- #
|
|
# --|-- | lo(mplier) * lo(mplicand) | #
|
|
# | ----------------------------- #
|
|
# ======================================================== #
|
|
# -------------------------------------------------------- #
|
|
# | hi(result) | lo(result) | #
|
|
# -------------------------------------------------------- #
|
|
#########################################################################
|
|
mulu64_alg:
|
|
# load temp registers with operands
|
|
mov.l %d0,%d2 # mr in d2
|
|
mov.l %d0,%d3 # mr in d3
|
|
mov.l %d1,%d4 # md in d4
|
|
swap %d3 # hi(mr) in lo d3
|
|
swap %d4 # hi(md) in lo d4
|
|
|
|
# complete necessary multiplies:
|
|
mulu.w %d1,%d0 # [1] lo(mr) * lo(md)
|
|
mulu.w %d3,%d1 # [2] hi(mr) * lo(md)
|
|
mulu.w %d4,%d2 # [3] lo(mr) * hi(md)
|
|
mulu.w %d4,%d3 # [4] hi(mr) * hi(md)
|
|
|
|
# add lo portions of [2],[3] to hi portion of [1].
|
|
# add carries produced from these adds to [4].
|
|
# lo([1]) is the final lo 16 bits of the result.
|
|
clr.l %d4 # load d4 w/ zero value
|
|
swap %d0 # hi([1]) <==> lo([1])
|
|
add.w %d1,%d0 # hi([1]) + lo([2])
|
|
addx.l %d4,%d3 # [4] + carry
|
|
add.w %d2,%d0 # hi([1]) + lo([3])
|
|
addx.l %d4,%d3 # [4] + carry
|
|
swap %d0 # lo([1]) <==> hi([1])
|
|
|
|
# lo portions of [2],[3] have been added in to final result.
|
|
# now, clear lo, put hi in lo reg, and add to [4]
|
|
clr.w %d1 # clear lo([2])
|
|
clr.w %d2 # clear hi([3])
|
|
swap %d1 # hi([2]) in lo d1
|
|
swap %d2 # hi([3]) in lo d2
|
|
add.l %d2,%d1 # [4] + hi([2])
|
|
add.l %d3,%d1 # [4] + hi([3])
|
|
|
|
# now, grab the condition codes. only one that can be set is 'N'.
|
|
# 'N' CAN be set if the operation is unsigned if bit 63 is set.
|
|
mov.w MUL64_CC(%a6),%d4
|
|
andi.b &0x10,%d4 # keep old 'X' bit
|
|
tst.l %d1 # may set 'N' bit
|
|
bpl.b mulu64_ddone
|
|
ori.b &0x8,%d4 # set 'N' bit
|
|
mulu64_ddone:
|
|
mov.w %d4,%cc
|
|
|
|
# here, the result is in d1 and d0. the current strategy is to save
|
|
# the values at the location pointed to by a0.
|
|
# use movm here to not disturb the condition codes.
|
|
mulu64_end:
|
|
exg %d1,%d0
|
|
movm.l &0x0003,([0x10,%a6]) # save result
|
|
|
|
# EPILOGUE BEGIN ########################################################
|
|
# fmovm.l (%sp)+,&0x0 # restore no fpregs
|
|
movm.l (%sp)+,&0x001c # restore d2-d4
|
|
unlk %a6
|
|
# EPILOGUE END ##########################################################
|
|
|
|
rts
|
|
|
|
# one or both of the operands is zero so the result is also zero.
|
|
# save the zero result to the register file and set the 'Z' ccode bit.
|
|
mulu64_zero:
|
|
clr.l %d0
|
|
clr.l %d1
|
|
|
|
mov.w MUL64_CC(%a6),%d4
|
|
andi.b &0x10,%d4
|
|
ori.b &0x4,%d4
|
|
mov.w %d4,%cc # set 'Z' ccode bit
|
|
|
|
bra.b mulu64_end
|
|
|
|
##########
|
|
# muls.l #
|
|
##########
|
|
global _060LSP__imuls64_
|
|
_060LSP__imuls64_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3c00,-(%sp) # save d2-d5
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,MUL64_CC(%a6) # save incomming ccodes
|
|
|
|
mov.l 0x8(%a6),%d0 # store multiplier in d0
|
|
beq.b mulu64_zero # handle zero separately
|
|
|
|
mov.l 0xc(%a6),%d1 # get multiplicand in d1
|
|
beq.b mulu64_zero # handle zero separately
|
|
|
|
clr.b %d5 # clear sign tag
|
|
tst.l %d0 # is multiplier negative?
|
|
bge.b muls64_chk_md_sgn # no
|
|
neg.l %d0 # make multiplier positive
|
|
|
|
ori.b &0x1,%d5 # save multiplier sgn
|
|
|
|
# the result sign is the exclusive or of the operand sign bits.
|
|
muls64_chk_md_sgn:
|
|
tst.l %d1 # is multiplicand negative?
|
|
bge.b muls64_alg # no
|
|
neg.l %d1 # make multiplicand positive
|
|
|
|
eori.b &0x1,%d5 # calculate correct sign
|
|
|
|
#########################################################################
|
|
# 63 32 0 #
|
|
# ---------------------------- #
|
|
# | hi(mplier) * hi(mplicand)| #
|
|
# ---------------------------- #
|
|
# ----------------------------- #
|
|
# | hi(mplier) * lo(mplicand) | #
|
|
# ----------------------------- #
|
|
# ----------------------------- #
|
|
# | lo(mplier) * hi(mplicand) | #
|
|
# ----------------------------- #
|
|
# | ----------------------------- #
|
|
# --|-- | lo(mplier) * lo(mplicand) | #
|
|
# | ----------------------------- #
|
|
# ======================================================== #
|
|
# -------------------------------------------------------- #
|
|
# | hi(result) | lo(result) | #
|
|
# -------------------------------------------------------- #
|
|
#########################################################################
|
|
muls64_alg:
|
|
# load temp registers with operands
|
|
mov.l %d0,%d2 # mr in d2
|
|
mov.l %d0,%d3 # mr in d3
|
|
mov.l %d1,%d4 # md in d4
|
|
swap %d3 # hi(mr) in lo d3
|
|
swap %d4 # hi(md) in lo d4
|
|
|
|
# complete necessary multiplies:
|
|
mulu.w %d1,%d0 # [1] lo(mr) * lo(md)
|
|
mulu.w %d3,%d1 # [2] hi(mr) * lo(md)
|
|
mulu.w %d4,%d2 # [3] lo(mr) * hi(md)
|
|
mulu.w %d4,%d3 # [4] hi(mr) * hi(md)
|
|
|
|
# add lo portions of [2],[3] to hi portion of [1].
|
|
# add carries produced from these adds to [4].
|
|
# lo([1]) is the final lo 16 bits of the result.
|
|
clr.l %d4 # load d4 w/ zero value
|
|
swap %d0 # hi([1]) <==> lo([1])
|
|
add.w %d1,%d0 # hi([1]) + lo([2])
|
|
addx.l %d4,%d3 # [4] + carry
|
|
add.w %d2,%d0 # hi([1]) + lo([3])
|
|
addx.l %d4,%d3 # [4] + carry
|
|
swap %d0 # lo([1]) <==> hi([1])
|
|
|
|
# lo portions of [2],[3] have been added in to final result.
|
|
# now, clear lo, put hi in lo reg, and add to [4]
|
|
clr.w %d1 # clear lo([2])
|
|
clr.w %d2 # clear hi([3])
|
|
swap %d1 # hi([2]) in lo d1
|
|
swap %d2 # hi([3]) in lo d2
|
|
add.l %d2,%d1 # [4] + hi([2])
|
|
add.l %d3,%d1 # [4] + hi([3])
|
|
|
|
tst.b %d5 # should result be signed?
|
|
beq.b muls64_done # no
|
|
|
|
# result should be a signed negative number.
|
|
# compute 2's complement of the unsigned number:
|
|
# -negate all bits and add 1
|
|
muls64_neg:
|
|
not.l %d0 # negate lo(result) bits
|
|
not.l %d1 # negate hi(result) bits
|
|
addq.l &1,%d0 # add 1 to lo(result)
|
|
addx.l %d4,%d1 # add carry to hi(result)
|
|
|
|
muls64_done:
|
|
mov.w MUL64_CC(%a6),%d4
|
|
andi.b &0x10,%d4 # keep old 'X' bit
|
|
tst.l %d1 # may set 'N' bit
|
|
bpl.b muls64_ddone
|
|
ori.b &0x8,%d4 # set 'N' bit
|
|
muls64_ddone:
|
|
mov.w %d4,%cc
|
|
|
|
# here, the result is in d1 and d0. the current strategy is to save
|
|
# the values at the location pointed to by a0.
|
|
# use movm here to not disturb the condition codes.
|
|
muls64_end:
|
|
exg %d1,%d0
|
|
movm.l &0x0003,([0x10,%a6]) # save result at (a0)
|
|
|
|
# EPILOGUE BEGIN ########################################################
|
|
# fmovm.l (%sp)+,&0x0 # restore no fpregs
|
|
movm.l (%sp)+,&0x003c # restore d2-d5
|
|
unlk %a6
|
|
# EPILOGUE END ##########################################################
|
|
|
|
rts
|
|
|
|
# one or both of the operands is zero so the result is also zero.
|
|
# save the zero result to the register file and set the 'Z' ccode bit.
|
|
muls64_zero:
|
|
clr.l %d0
|
|
clr.l %d1
|
|
|
|
mov.w MUL64_CC(%a6),%d4
|
|
andi.b &0x10,%d4
|
|
ori.b &0x4,%d4
|
|
mov.w %d4,%cc # set 'Z' ccode bit
|
|
|
|
bra.b muls64_end
|
|
|
|
#########################################################################
|
|
# XDEF **************************************************************** #
|
|
# _060LSP__cmp2_Ab_(): Emulate "cmp2.b An,<ea>". #
|
|
# _060LSP__cmp2_Aw_(): Emulate "cmp2.w An,<ea>". #
|
|
# _060LSP__cmp2_Al_(): Emulate "cmp2.l An,<ea>". #
|
|
# _060LSP__cmp2_Db_(): Emulate "cmp2.b Dn,<ea>". #
|
|
# _060LSP__cmp2_Dw_(): Emulate "cmp2.w Dn,<ea>". #
|
|
# _060LSP__cmp2_Dl_(): Emulate "cmp2.l Dn,<ea>". #
|
|
# #
|
|
# This is the library version which is accessed as a subroutine #
|
|
# and therefore does not work exactly like the 680X0 "cmp2" #
|
|
# instruction. #
|
|
# #
|
|
# XREF **************************************************************** #
|
|
# None #
|
|
# #
|
|
# INPUT *************************************************************** #
|
|
# 0x4(sp) = Rn #
|
|
# 0x8(sp) = pointer to boundary pair #
|
|
# #
|
|
# OUTPUT ************************************************************** #
|
|
# cc = condition codes are set correctly #
|
|
# #
|
|
# ALGORITHM *********************************************************** #
|
|
# In the interest of simplicity, all operands are converted to #
|
|
# longword size whether the operation is byte, word, or long. The #
|
|
# bounds are sign extended accordingly. If Rn is a data regsiter, Rn is #
|
|
# also sign extended. If Rn is an address register, it need not be sign #
|
|
# extended since the full register is always used. #
|
|
# The condition codes are set correctly before the final "rts". #
|
|
# #
|
|
#########################################################################
|
|
|
|
set CMP2_CC, -4
|
|
|
|
global _060LSP__cmp2_Ab_
|
|
_060LSP__cmp2_Ab_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.b ([0xc,%a6],0x0),%d0
|
|
mov.b ([0xc,%a6],0x1),%d1
|
|
|
|
extb.l %d0 # sign extend lo bnd
|
|
extb.l %d1 # sign extend hi bnd
|
|
bra.w l_cmp2_cmp # go do the compare emulation
|
|
|
|
global _060LSP__cmp2_Aw_
|
|
_060LSP__cmp2_Aw_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.w ([0xc,%a6],0x0),%d0
|
|
mov.w ([0xc,%a6],0x2),%d1
|
|
|
|
ext.l %d0 # sign extend lo bnd
|
|
ext.l %d1 # sign extend hi bnd
|
|
bra.w l_cmp2_cmp # go do the compare emulation
|
|
|
|
global _060LSP__cmp2_Al_
|
|
_060LSP__cmp2_Al_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.l ([0xc,%a6],0x0),%d0
|
|
mov.l ([0xc,%a6],0x4),%d1
|
|
bra.w l_cmp2_cmp # go do the compare emulation
|
|
|
|
global _060LSP__cmp2_Db_
|
|
_060LSP__cmp2_Db_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.b ([0xc,%a6],0x0),%d0
|
|
mov.b ([0xc,%a6],0x1),%d1
|
|
|
|
extb.l %d0 # sign extend lo bnd
|
|
extb.l %d1 # sign extend hi bnd
|
|
|
|
# operation is a data register compare.
|
|
# sign extend byte to long so we can do simple longword compares.
|
|
extb.l %d2 # sign extend data byte
|
|
bra.w l_cmp2_cmp # go do the compare emulation
|
|
|
|
global _060LSP__cmp2_Dw_
|
|
_060LSP__cmp2_Dw_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.w ([0xc,%a6],0x0),%d0
|
|
mov.w ([0xc,%a6],0x2),%d1
|
|
|
|
ext.l %d0 # sign extend lo bnd
|
|
ext.l %d1 # sign extend hi bnd
|
|
|
|
# operation is a data register compare.
|
|
# sign extend word to long so we can do simple longword compares.
|
|
ext.l %d2 # sign extend data word
|
|
bra.w l_cmp2_cmp # go emulate compare
|
|
|
|
global _060LSP__cmp2_Dl_
|
|
_060LSP__cmp2_Dl_:
|
|
|
|
# PROLOGUE BEGIN ########################################################
|
|
link.w %a6,&-4
|
|
movm.l &0x3800,-(%sp) # save d2-d4
|
|
# fmovm.l &0x0,-(%sp) # save no fpregs
|
|
# PROLOGUE END ##########################################################
|
|
|
|
mov.w %cc,CMP2_CC(%a6)
|
|
mov.l 0x8(%a6), %d2 # get regval
|
|
|
|
mov.l ([0xc,%a6],0x0),%d0
|
|
mov.l ([0xc,%a6],0x4),%d1
|
|
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#
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# To set the ccodes correctly:
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# (1) save 'Z' bit from (Rn - lo)
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# (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
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# (3) keep 'X', 'N', and 'V' from before instruction
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# (4) combine ccodes
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#
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l_cmp2_cmp:
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sub.l %d0, %d2 # (Rn - lo)
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mov.w %cc, %d3 # fetch resulting ccodes
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andi.b &0x4, %d3 # keep 'Z' bit
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sub.l %d0, %d1 # (hi - lo)
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cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
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mov.w %cc, %d4 # fetch resulting ccodes
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or.b %d4, %d3 # combine w/ earlier ccodes
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andi.b &0x5, %d3 # keep 'Z' and 'N'
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mov.w CMP2_CC(%a6), %d4 # fetch old ccodes
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andi.b &0x1a, %d4 # keep 'X','N','V' bits
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or.b %d3, %d4 # insert new ccodes
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mov.w %d4,%cc # save new ccodes
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# EPILOGUE BEGIN ########################################################
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# fmovm.l (%sp)+,&0x0 # restore no fpregs
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movm.l (%sp)+,&0x001c # restore d2-d4
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unlk %a6
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# EPILOGUE END ##########################################################
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rts
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