47fa5a292f
576000bps and 1152000bps. In the current published version of the data sheet the MIR support documentation is gone, and the MIR mode bit is documented as reserved. Possibly the device has a design flaw affecting the MIR data rates? Document here that this information came from an earlier data sheet, but leave MIR support in for the moment.
187 lines
6.1 KiB
C
187 lines
6.1 KiB
C
/* $NetBSD: ustirreg.h,v 1.3 2002/12/28 06:04:18 dsainty Exp $ */
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/*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by David Sainty <David.Sainty@dtsp.co.nz>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Registers definitions for SigmaTel STIr4200 USB/IrDA Bridge
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* Controller. Documentation available at:
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* http://www.sigmatel.com/technical_docs.htm
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* http://extranet.sigmatel.com/library/infrared/stir4200/stir4200-ds-1-0.pdf
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*/
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/* Notes:
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*
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* The data sheet states that the TX and RX frames are prepended with
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* BOF characters. This appears to be incorrect, the standard 0xff
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* characters behave as expected.
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*
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* There does not appear to be any way to get asynchronous
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* notifications from this device that data is waiting. You simply do
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* have to poll continuously looking for a non-zero-length result.
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*
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* The SigmaTel drivers provided with the device for other operating
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* systems poll at full USB speed (1000 per second), which has a
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* significant impact on the system.
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*/
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/*
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* The SigmaTel device is controlled via an array of registers, with
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* generic register read/write commands. This is a completely
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* different approach to that defined in the USB IrDA standard.
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*/
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#define STIR_REG_MODE 1
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#define STIR_REG_BRATE 2
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#define STIR_REG_CONTROL 3
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#define STIR_REG_SENSITIVITY 4
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#define STIR_REG_STATUS 5
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#define STIR_REG_FFCNT_LSB 6
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#define STIR_REG_FFCNT_MSB 7
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#define STIR_REG_DPLL 8
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#define STIR_REG_IRDIG 9
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/* Register numbers range from zero to STIR_MAX_REG */
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#define STIR_MAX_REG 15
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/*
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* Mode register bits
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*
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* The MIR bit was documented in earlier revisions of the data sheet,
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* but in the current published version (version 1.0, March 2002) the
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* MIR bit is documented as "reserved". Possibly the device has a
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* design flaw affecting the MIR data rates.
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*/
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#define STIR_RMODE_FIR 0x80
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#define STIR_RMODE_MIR 0x40
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#define STIR_RMODE_SIR 0x20
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#define STIR_RMODE_ASK 0x10
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/*
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* FASTRXEN can be set to enable simultaneous reads and writes. It
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* isn't clear that this is useful, the RX and TX data is mixed into
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* the FIFO and the chip appears to get into a funny state. In the
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* absence of good documentation about this bit, leave it disabled!
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*/
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#define STIR_RMODE_FASTRXEN 0x08
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#define STIR_RMODE_FFRSTEN 0x04
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/* FFSPRST must be set to enable the FIFO */
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#define STIR_RMODE_FFSPRST 0x02
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/*
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* High bit baud rate generator value, used in conjunction with the
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* BRATE register.
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*/
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#define STIR_RMODE_PDCLK8 0x01
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/* Status register bits */
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#define STIR_RSTATUS_EOFRAME 0x80
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#define STIR_RSTATUS_FFUNDER 0x40
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#define STIR_RSTATUS_FFOVER 0x20
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/* Set in write direction, cleared in read direction */
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#define STIR_RSTATUS_FFDIR 0x10
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/*
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* FFCLR is write-only, and the only writable bit in the STATUS
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* register.
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*/
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#define STIR_RSTATUS_FFCLR 0x08
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#define STIR_RSTATUS_FFEMPTY 0x04
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#define STIR_RSTATUS_FFRXERR 0x02
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#define STIR_RSTATUS_FFTXERR 0x01
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/* Extract data from portions of registers */
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#define STIR_GET_SENSITIVITY_CHIPREVISION(x) ((x) & 7)
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/*
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* According to the documentation, FFCNT may be off by as much as 3
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* bytes.
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*/
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#define STIR_FFCNT_MARGIN 3
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/*
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* The FIFO size for the device is a fixed 4k bytes
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*/
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#define STIR_FIFO_SIZE 0x1000
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/*
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* Vendor specific device requests
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*/
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#define STIR_CMD_WRITEMULTIREG 0x00
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#define STIR_CMD_READMULTIREG 0x01
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#define STIR_CMD_READROM 0x02
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#define STIR_CMD_WRITESINGLEREG 0x03
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/*
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* The MSB is the MODE register setting, the LSB is the BRATE register
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* setting.
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*
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* The MIR rates (576000 and 1152000) were documented in earlier
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* revisions of the data sheet, but in the current published version
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* these data rates have disappeared. Possibly the device has a
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* design flaw affecting the MIR data rates.
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*/
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#define STIR_BRMODE_4000000 0x8002
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#define STIR_BRMODE_1152000 0x4001
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#define STIR_BRMODE_576000 0x4003
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#define STIR_BRMODE_115200 0x2009
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#define STIR_BRMODE_57600 0x2013
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#define STIR_BRMODE_38400 0x201d
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#define STIR_BRMODE_19200 0x203b
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#define STIR_BRMODE_9600 0x2077
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#define STIR_BRMODE_2400 0x21df
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/*
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* Extract values from STIR_BRMODE values.
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*/
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#define STIR_BRMODE_MODEREG(x) ((x) >> 8)
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#define STIR_BRMODE_BRATEREG(x) ((x) & 0xff)
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/*
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* Each transmit frame starts with the sequence:
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*
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* 0x55 0xaa LSB(Length) MSB(Length)
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*/
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#define STIR_OUTPUT_HEADER_SIZE 4
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#define STIR_OUTPUT_HEADER_BYTE0 0x55
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#define STIR_OUTPUT_HEADER_BYTE1 0xaa
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