99 lines
4.4 KiB
C
99 lines
4.4 KiB
C
/* $NetBSD: siopvar.h,v 1.16 2001/04/25 17:53:34 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* structure and definitions for the siop driver */
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TAILQ_HEAD(cmd_list, siop_cmd);
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TAILQ_HEAD(cbd_list, siop_cbd);
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TAILQ_HEAD(lunsw_list, siop_lunsw);
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/* Driver internal state */
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struct siop_softc {
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struct device sc_dev;
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struct scsipi_channel sc_chan;
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struct scsipi_adapter sc_adapt;
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int features; /* chip's features */
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int ram_size;
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int maxburst;
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int maxoff;
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int clock_div; /* async. clock divider (scntl3) */
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int clock_period; /* clock period (ns * 10) */
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int minsync; /* min and max sync period, */
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int maxsync; /* as sent in SDTR message */
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bus_space_tag_t sc_rt; /* bus_space registers tag */
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bus_space_handle_t sc_rh; /* bus_space registers handle */
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bus_addr_t sc_raddr; /* register adresses */
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bus_space_tag_t sc_ramt; /* bus_space ram tag */
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bus_space_handle_t sc_ramh; /* bus_space ram handle */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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void (*sc_reset) __P((struct siop_softc*)); /* reset callback */
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bus_dmamap_t sc_scriptdma; /* DMA map for script */
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bus_addr_t sc_scriptaddr; /* on-board ram or physical adress */
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u_int32_t *sc_script; /* script location in memory */
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int sc_currschedslot; /* current scheduler slot */
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struct cbd_list cmds; /* list of command block descriptors */
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struct cmd_list free_list; /* cmd descr free list */
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struct lunsw_list lunsw_list; /* lunsw free list */
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u_int32_t script_free_lo; /* free ram offset from sc_scriptaddr */
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u_int32_t script_free_hi; /* free ram offset from sc_scriptaddr */
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struct siop_target *targets[16]; /* per-target states */
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int sc_ntargets; /* number of known targets */
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u_int32_t sc_flags;
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};
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/* defs for sc_flags */
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#define SCF_CHAN_NOSLOT 0x0001 /* channel out of sheduler slot */
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/* features */
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#define SF_BUS_WIDE 0x00000001 /* wide bus */
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#define SF_BUS_ULTRA 0x00000002 /* Ultra (20Mhz) bus */
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#define SF_BUS_ULTRA2 0x00000004 /* Ultra2 (40Mhz) bus */
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#define SF_BUS_DIFF 0x00000008 /* differential bus */
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#define SF_CHIP_LED0 0x00000100 /* led on GPIO0 */
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#define SF_CHIP_DBLR 0x00000200 /* clock doubler or quadrupler */
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#define SF_CHIP_QUAD 0x00000400 /* clock quadrupler, with PPL */
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#define SF_CHIP_FIFO 0x00000800 /* large fifo */
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#define SF_CHIP_PF 0x00001000 /* Intructions prefetch */
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#define SF_CHIP_RAM 0x00002000 /* on-board RAM */
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#define SF_CHIP_LS 0x00004000 /* load/store instruction */
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#define SF_CHIP_10REGS 0x00008000 /* 10 scratch registers */
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#define SF_CHIP_DFBC 0x00010000 /* Use DFBC register */
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#define SF_PCI_RL 0x01000000 /* PCI read line */
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#define SF_PCI_RM 0x02000000 /* PCI read multiple */
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#define SF_PCI_BOF 0x04000000 /* PCI burst opcode fetch */
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#define SF_PCI_CLS 0x08000000 /* PCI cache line size */
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#define SF_PCI_WRI 0x10000000 /* PCI write and invalidate */
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void siop_attach __P((struct siop_softc *));
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int siop_intr __P((void *));
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