215 lines
8.1 KiB
C
215 lines
8.1 KiB
C
/* $NetBSD: adwmcode.h,v 1.7 2001/08/29 17:25:04 briggs Exp $ */
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/*
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* Generic driver definitions and exported functions for the Advanced
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* Systems Inc. SCSI controllers
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*
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* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Author: Baldassare Dante Profeta <dante@mclink.it>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ADW_MCODE_H
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#define ADW_MCODE_H
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/******************************************************************************/
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#define ADW_MAX_CARRIER 253 /* Max. number of host commands (253) */
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/*
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* ADW_CARRIER must be exactly 16 BYTES
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* Every adw_carrier structure _MUST_ always be aligned on a 16 bytes boundary
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*/
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struct adw_carrier {
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/* ---------- the microcode wants the field below ---------- */
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u_int32_t carr_id; /* Carrier ID */
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u_int32_t carr_ba; /* Carrier Bus Address */
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u_int32_t areq_ba; /* ADW_SCSI_REQ_Q Bus Address */
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/*
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* next_ba [31:4] Carrier Physical Next Pointer
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*
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* next_ba [3:1] Reserved Bits
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* next_ba [0] Done Flag set in Response Queue.
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*/
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u_int32_t next_ba; /* see next_ba flags below */
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/* ---------- ---------- */
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};
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typedef struct adw_carrier ADW_CARRIER;
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/*
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* next_ba flags
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*/
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#define ASC_RQ_DONE 0x00000001
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#define ASC_RQ_GOOD 0x00000002
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#define ASC_CQ_STOPPER 0x00000000
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/*
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* Mask used to eliminate low 4 bits of carrier 'next_ba' field.
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*/
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#define ASC_NEXT_BA_MASK 0xFFFFFFF0
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#define ASC_GET_CARRP(carrp) htole32((le32toh(carrp)) & ASC_NEXT_BA_MASK)
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/*
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* Bus Address of a Carrier.
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* ba = base_ba + v_address - base_va
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*/
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#define ADW_CARRIER_BADDR(dmamap, carriers, x) \
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htole32((dmamap)->dm_segs[0].ds_addr + ((u_long)x - (u_long)(carriers)))
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/*
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* Virtual Address of a Carrier.
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* va = base_va + bus_address - base_ba
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*/
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#define ADW_CARRIER_VADDR(sc, x) ((ADW_CARRIER *) \
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(((u_int8_t *)(sc)->sc_control->carriers) + \
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le32toh((u_long)x) - \
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(sc)->sc_dmamap_carrier->dm_segs[0].ds_addr))
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/******************************************************************************/
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struct adw_mcode {
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const u_int8_t * const mcode_data;
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const u_int32_t mcode_chksum;
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const u_int16_t mcode_size;
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};
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/******************************************************************************/
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/*
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* Fixed locations of microcode operating variables.
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*/
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#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
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#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
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#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
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#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
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#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
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#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
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#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
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#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
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#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
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#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
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#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
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#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
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#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
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/*
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* 4-bit speed SDTR speed name
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* =========== ===============
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* 0000b (0x0) SDTR disabled
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* 0001b (0x1) 5 Mhz
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* 0010b (0x2) 10 Mhz
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* 0011b (0x3) 20 Mhz (Ultra)
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* 0100b (0x4) 40 Mhz (LVD/Ultra2)
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* 0101b (0x5) 80 Mhz (LVD2/Ultra3)
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* 0110b (0x6) Undefined
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* ...
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* 1111b (0xF) Undefined
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*/
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#define ADW_MC_CHIP_TYPE 0x009A
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#define ADW_MC_INTRB_CODE 0x009B
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#define ADW_MC_WDTR_ABLE 0x009C
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#define ADW_MC_SDTR_ABLE 0x009E
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#define ADW_MC_TAGQNG_ABLE 0x00A0
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#define ADW_MC_DISC_ENABLE 0x00A2
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#define ADW_MC_IDLE_CMD_STATUS 0x00A4
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#define ADW_MC_IDLE_CMD 0x00A6
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#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8
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#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
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#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
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#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
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#define ADW_MC_DEFAULT_SEL_MASK 0x00B2
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#define ADW_MC_SDTR_DONE 0x00B6
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#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0
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#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
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#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
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#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
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#define ADW_MC_WDTR_DONE 0x0124
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#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
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#define ADW_MC_ICQ 0x0160
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#define ADW_MC_IRQ 0x0164
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#define ADW_MC_PPR_ABLE 0x017A
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/*
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* Microcode Control Flags
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*
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* Flags set by the Adw Library in RISC variable 'control_flag' (0x122)
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* and handled by the microcode.
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*/
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#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
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#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
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/*
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* ADW_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
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*/
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#define HSHK_CFG_WIDE_XFR 0x8000
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#define HSHK_CFG_RATE 0x0F00
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#define HSHK_CFG_OFFSET 0x001F
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#define ADW_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
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#define ADW_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
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#define ADW_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
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#define ADW_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
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#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */
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#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
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#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
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#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
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#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXX TBD*/
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#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
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#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
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#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
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#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
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#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
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/*
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* Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
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* ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
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*/
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#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
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#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
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/******************************************************************************/
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ADW_CARRIER *AdwInitCarriers __P((bus_dmamap_t, ADW_CARRIER *));
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extern const struct adw_mcode adw_asc3550_mcode_data;
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extern const struct adw_mcode adw_asc38C0800_mcode_data;
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extern const struct adw_mcode adw_asc38C1600_mcode_data;
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/******************************************************************************/
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#endif /* ADW_MCODE_H */
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