170 lines
5.3 KiB
C
170 lines
5.3 KiB
C
/* $NetBSD: r3900regs.h,v 1.4 2000/08/24 05:31:59 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* [address space]
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* kseg2 0xc0000000 - 0xfeffffff
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* reserved 0xff000000 - 0xfffeffff
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* kseg2 0xffff0000 - 0xffffffff
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* -> vmparam.h VM_MAX_KERNEL_ADDRESS
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*/
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/*
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* [cause register]
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*/
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#define R3900_CR_EXC_CODE MIPS3_CR_EXC_CODE /* five bits */
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#undef MIPS1_CR_EXC_CODE
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#define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE
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/*
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* [status register]
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* R3900 don't have PE, CM, PZ, SwC and IsC.
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*/
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#define R3900_SR_NMI 0x00100000 /* r3k PE position */
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#undef MIPS1_PARITY_ERR
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#undef MIPS1_CACHE_MISS
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#undef MIPS1_PARITY_ZERO
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#undef MIPS1_SWAP_CACHES
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#undef MIPS1_ISOL_CACHES
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/*
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* [context register]
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* - no changes.
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*/
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/*
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* TX3900 Coprocessor 0 registers
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*/
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#define R3900_COP_0_CONFIG $3
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#define R3900_COP_0_DEBUG $16
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#define R3900_COP_0_DEPC $17
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#define R3920_COP_0_PAGEMASK $5
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#define R3920_COP_0_WIRED $6
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#define R3920_COP_0_CACHE $7
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#define R3920_COP_0_TAG_LO $20
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/*
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* TLB entry
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* 3912 ... TLB entry is 64bits wide and R3000A compatible
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* 3922 ... TLB entry is 96bits wide
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*/
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/*
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* Index register
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* 3912 ... index field[8:12] (32 entry)
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*/
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#define R3900_TLB_NUM_TLB_ENTRIES 32
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#define R3920_TLB_NUM_TLB_ENTRIES 64
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#undef MIPS1_TLB_NUM_TLB_ENTRIES
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#ifdef TX391X
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#define MIPS1_TLB_NUM_TLB_ENTRIES R3900_TLB_NUM_TLB_ENTRIES
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#elif defined TX392X
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#define MIPS1_TLB_NUM_TLB_ENTRIES R3920_TLB_NUM_TLB_ENTRIES
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#endif
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/*
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* Config register (R3900 specific)
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*/
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#define R3900_CONFIG_ICS_SHIFT 19
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#define R3900_CONFIG_ICS_MASK 0x00380000
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#define R3900_CONFIG_ICS_1KB 0x00000000
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#define R3900_CONFIG_ICS_2KB 0x00080000
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#define R3900_CONFIG_ICS_4KB 0x00100000
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#define R3900_CONFIG_ICS_8KB 0x00180000
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#define R3900_CONFIG_ICS_16KB 0x00200000
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#define R3900_CONFIG_DCS_SHIFT 16
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#define R3900_CONFIG_DCS_1KB 0x00000000
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#define R3900_CONFIG_DCS_2KB 0x00010000
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#define R3900_CONFIG_DCS_4KB 0x00020000
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#define R3900_CONFIG_DCS_8KB 0x00030000
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#define R3900_CONFIG_DCS_16KB 0x00040000
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#define R3900_CONFIG_DCS_MASK 0x00070000
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#define R3900_CONFIG_CWFON 0x00004000
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#define R3900_CONFIG_WBON 0x00002000
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#define R3900_CONFIG_RF_SHIFT 10
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#define R3900_CONFIG_RF_MASK 0x00000c00
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#define R3900_CONFIG_DOZE 0x00000200
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#define R3900_CONFIG_HALT 0x00000100
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#define R3900_CONFIG_LOCK 0x00000080
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#define R3900_CONFIG_ICE 0x00000020
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#define R3900_CONFIG_DCE 0x00000010
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#define R3900_CONFIG_IRSIZE_SHIFT 2
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#define R3900_CONFIG_IRSIZE_MASK 0x0000000c
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#define R3900_CONFIG_DRSIZE_SHIFT 0
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#define R3900_CONFIG_DRSIZE_MASK 0x00000003
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/*
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* CACHE
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*/
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/* Cache size (limit) */
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/* R3900/R3920 */
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#define R3900_C_SIZE_MIN 1024
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#define R3900_C_SIZE_MAX 8192
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/* Cache line size */
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/* R3900 */
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#define R3900_C_LSIZE_I 16
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#define R3900_C_LSIZE_D 4
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/* R3920 */
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#define R3920_C_LSIZE_I 16
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#define R3920_C_LSIZE_D 16
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/* Cache operation */
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/* R3900 */
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#define R3900_C_IINV_I 0x00
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#define R3900_C_IWBINV_D 0x01
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#define R3900_C_ILRUC_I 0x04
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#define R3900_C_ILRUC_D 0x05
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#define R3900_C_ILCKC_D 0x09 /* R3900 only */
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#define R3900_C_HINV_D 0x11
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/* R3920 */
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#define R3920_C_IINV_I 0x00
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#define R3920_C_IWBINV_D 0x01
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#define R3920_C_ILRUC_I 0x04
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#define R3920_C_ILRUC_D 0x05
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#define R3920_C_ILDTAG_I 0x0c /* R3920 only */
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#define R3920_C_ILDTAG_D 0x0d /* R3920 only */
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#define R3920_C_HINV_I 0x10 /* R3920 only */
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#define R3920_C_HINV_D 0x11
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#define R3920_C_HWBINV_D 0x14 /* R3920 only */
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#define R3920_C_HWB_D 0x18 /* R3920 only */
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#define R3920_C_ISTTAG_I 0x1c /* R3920 only */
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#define R3920_C_ISTTAG_D 0x1d /* R3920 only */
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