78037d3f6d
- generic soft interrupts (ie. use powerpc/softintr.c) - interrupt event counters (using the ones from powerpc/cpu.h:cpu_info where appropriate) - cleanup ibm4xx_intr.h, move implementation details to intr.c Convert all affected evbppc platforms. OK by simonb@, some points discussed with matt@
213 lines
4.4 KiB
ArmAsm
213 lines
4.4 KiB
ArmAsm
/* $NetBSD: explora_start.S,v 1.4 2006/06/30 17:54:50 freza Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Juergen Hannken-Illjes.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Initial state:
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*
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* iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
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* dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
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* dcwr = 0x00000000
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* msr = 0x00001000 ME=machine check enable
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*
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*/
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#include "assym.h"
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#define _NOREGNAMES
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#include <machine/param.h>
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/asm.h>
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/dcr403cgx.h>
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#include <powerpc/ibm4xx/pmap.h>
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#include "opt_ddb.h"
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#include "opt_ppcparam.h"
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GLOBAL(proc0paddr)
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.long 0 /* proc0 p_addr */
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/*
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* Initially the dram starts at 0x01000000. This is way too high.
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* We relocate dram to 0x00000000. We use the video ram at 0xf0000000
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* as a temporary staging area.
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*/
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#define STAGE1_BASE 0xf0000000
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.text
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.globl __start
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__start:
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b 1f
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nop
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nop
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.long 0
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.ascii "XncdPPC\0"
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.long 0
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.long 0
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1:
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/* Disable exceptions, caches, invalidate all TLB's. */
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li 0,0
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mtmsr 0
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mttcr 0
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mtdccr 0
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mticcr 0
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sync
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isync
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/* Clear caches and invalidate tlbs */
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li 7,256
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mtctr 7
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li 6,0
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1:
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dccci 0,6
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addi 6,6,16
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bdnz 1b
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li 7,512
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mtctr 7
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li 6,0
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1:
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iccci 0,6
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addi 6,6,16
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bdnz 1b
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tlbia
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sync
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isync
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/* Get current address -- NOT the same as . */
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bl _next
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_next:
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mflr 3
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subi 3,3,_next-__start
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lis 4,STAGE1_BASE@h
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ori 4,4,STAGE1_BASE@l
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li 5,stage1size
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1:
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lbz 1,0(3)
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mr 0,5
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cmpwi 0,0
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stb 1,0(4)
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addi 3,3,1
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addi 4,4,1
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addi 5,5,-1
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bgt 1b
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/* Jump into the staging area so we can remap the dram. */
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lis 0,stage1reloc@h
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ori 0,0,stage1reloc@l
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mtlr 0
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blr
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stage1reloc = .-__start+STAGE1_BASE
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/* Remap the dram from 0x01000000 to 0x00000000. */
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#define REMAP(r, tmp1, tmp2) \
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mfbr##r tmp1 ; \
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lis tmp2,0xff ; \
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ori tmp2,tmp2,0xffff ; \
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cmplw tmp1,tmp2 ; \
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ble 1f ; \
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addis tmp1,tmp1,0xf000 ; \
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mtbr##r tmp1 ; \
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1:
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REMAP(4, 1, 2)
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REMAP(5, 1, 2)
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REMAP(6, 1, 2)
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REMAP(7, 1, 2)
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#undef REMAP
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/* Initial setup. */
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ba stage2
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stage2:
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#ifdef PPC_4XX_NOCACHE
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li 0,0
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#else
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lis 0,0xfffc
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#endif
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mtdccr 0
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mticcr 0
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sync
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isync
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/* get start of bss */
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lis 7,_C_LABEL(edata)-4@h
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ori 7,7,_C_LABEL(edata)-4@l
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/* get end of kernel */
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lis 4,_C_LABEL(end)@h
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ori 4,4,_C_LABEL(end)@l
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/* clear bss */
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li 3,0
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1:
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stwu 3,4(7)
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cmpw 7,4
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bne+ 1b
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INIT_CPUINFO(4,1,9,0)
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lis 3,__start@h
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ori 3,3,__start@l
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/* Run the remaining setup in C. */
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bl _C_LABEL(bootstrap)
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bl _C_LABEL(main)
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/* NOTREACHED */
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2: nop
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b 2b
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stage1size = .-__start
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#include <powerpc/ibm4xx/4xx_locore.S>
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