0e11c6bfd5
opencrypto by CoyotePoint Systems. The FreeBSD driver source was recently made available by NBMK Encryption Technologies. The port includes some currently unused code which implements kernel and user space interfaces for the driver in FreeBSD. These are left in at this time to facilitate the port of these interface to NetBSD if they are of interest.
918 lines
34 KiB
C
918 lines
34 KiB
C
/*-
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* Copyright (C) 2001-2003 by NBMK Encryption Technologies.
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* All rights reserved.
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*
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* NBMK Encryption Technologies provides no support of any kind for
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* this software. Questions or concerns about it may be addressed to
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* the members of the relevant open-source community at
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* <tech-crypto@netbsd.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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static char const n8_id[] = "$Id: irq.c,v 1.1 2008/10/30 12:02:14 darran Exp $";
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/*****************************************************************************/
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/** @file irq.c
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* @brief NSP2000 Device Driver interrupt handling functions
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*
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* This file contains all secondary interrupt handling routines for the
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* NSP2000 Device Driver.
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*
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*****************************************************************************/
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/*****************************************************************************
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* Revision history:
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* 01/06/04 brr Clear the PKH & CCH status register prior to reading queue
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* pointer register to ensure write completes before exiting the
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* interrupt handler. Only write AMBA status register on AMBA
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* timer interrupts. (Bug 995)
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* 07/15/03 brr Moved CCH processing to a Linux tasklet.
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* 07/01/03 brr Clear CCH interrupts before reenabling the core.
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* 05/15/03 brr Enable RNG interrupt, remove references to duplicate register
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* definitions in irq.h
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* 04/08/03 brr Bypass AMBA mirror registers.
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* 04/03/03 brr Minor modifications to improve performance.
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* 04/01/03 brr Reverted N8_WaitOnRequest to accept timeout parameter.
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* 03/31/03 brr Do not rely on atomic_inc_and_test.
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* 03/24/03 brr Fix race condition when conditionally resetting AMBA timer.
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* 03/21/03 brr Only check for completed EA commands on AMBA timer interrupt.
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* 03/19/03 brr Added Interrupt statistics and display function, eliminating
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* IRQ prints. Added reload_AMBA_timer function in order support
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* running AMBA timer only when there are requests queued.
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* Modified and moved N8_WaitOnRequest to QMGR.
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* 03/18/03 brr Do not read PKH/CCH status register if no errors are reported
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* in the AMBA status registers, assume command complete.
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* 02/02/03 brr Updated command completion determination to use the number
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* of commands completed instead of queue position. This
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* elimated the need for forceCheck & relying on the request
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* state to avoid prematurely marking a command complete.
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* 12/09/02 brr Remove duplicate read in of read index in CCHInterrupt.
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* 11/01/02 brr Reinstate forceCheck.
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* 10/23/02 brr Remove forceCheck since interrupts are now disabled during
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* the queue operation.
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* 10/25/02 brr Clean up function prototypes & include files.
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* 10/11/02 brr Added timeout parameter to N8_WaitOnRequest.
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* 09/18/02 brr Added N8_WaitOnRequest & modified ISR to keep track of the
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* number of requests completed.
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* 09/10/02 brr Modified PKH & CCH interrupt service routines to handle the
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* command completion interrupt.
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* 06/10/02 brr Call QMgrCheckQueue if forceCheck is set.
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* 06/05/02 mmd Eliminated unused debug messages, and ensured that when
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* waitOnInterrupt is called with interruptible == FALSE,
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* that AMBAbitmask is updated with the specified bitmask.
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* 05/30/02 brr Enable interrupts for error conditions and handle them in the
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* ISR.
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* 05/20/02 brr Revert to a single AMBA wait queue.
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* 04/30/02 brr Minor revisions to improve performance & incorporate comments
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* from code review.
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* 04/17/02 msz Don't call QMgr if there is nothing new done.
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* 04/15/02 hml Added a call to N8_DOWN_KERNELSEM when we get an AMBA
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* interrupt in kernel mode.
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* 04/11/02 brr Pass parameter to waitOnInterrupt to indicate whether
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* sleep should be interruptable.
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* 04/03/02 brr Fix spurious interrupt by clearing the interrupt before
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* reading the amba_pci_control.
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* 03/19/02 msz Shadow memory is now called shared memory.
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* 02/26/02 brr Modified the timer interrupt to update the queue pointers
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* and complete the API requests.
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* 02/27/02 msz Fixes for N8_WaitOnInterrupt support.
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* 02/22/02 spm Converted printk's to DBG's. Added #include of n8_OS_intf.h
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* 02/22/02 brr Removed references to qmgrData.
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* 02/22/02 msz Fix for BUG 620, CCH should be using the EAshadow_p
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* 02/15/02 brr Removed FPGA references.
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* 02/06/02 msz Moved where we set shadow hw status.
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* 01/31/02 brr On error, save status to shared memory.
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* 01/15/02 msz Support for array of AMBA wait blocks. Also we now always
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* do the wakeup call for AMBA interrupts once something has
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* waited on an AMBA interrupt.
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* 01/03/02 brr Reset bridge timer upon expiration.
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* 01/16/02 brr Removed FPGA support.
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* 12/03/01 mmd Accidentally always performing 11-12 PCI accesses when using
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* ASIC, regardless of whether or not we have an IRQ.
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* 11/30/01 mmd Forgot to wrap LCR manipulation with check for FPGA.
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* 11/27/01 mmd Eliminated N8_EnableInterrupts. Modified
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* n8_MainInterruptHandler to only bother with PLX if FPGA.
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* Beyond that, everything is and should be treated identically.
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* Renamed from simon_irq.c.
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* 11/10/01 brr Modified to support static allocations of persistant data
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* by the driver.
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* 10/17/01 mmd Revised all debug messages to use N8_IRQprint/N8_IRQPRINT
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* except for N8_EnableInterrupts and n8_WaitOnInterrupt,
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* neither of which are called from Interrupt time.
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* 10/12/01 mmd In n8_WaitOnInterrupt, corrected handling of return values
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* from N8_BlockWithTimeout.
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* 09/24/01 mmd Added support in n8_WaitOnInterrupt and
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* N8_MainInterruptHandler for AMBA interrupts, and adjusted
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* return values for n8_WaitOnInterrupt. Corrected bug where
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* the return code from N8_BlockWithTimeout was being
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* misinterpreted. Updated call to N8_BlockWithTimeout, when
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* passing a wait_queue_head_t* type.
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* 09/20/01 mmd Implemented N8_MainInterruptHandler.
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* 09/07/01 mmd Cleanup and revision of WaitOnInterrupt routine.
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* 08/16/01 mmd No longer includes n8_types.h.
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* 08/16/01 mmd Now includes nsp2000_regs.h instead of simon.h..
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* 08/08/01 brr Moved all OS kernel specific macros to helper.h.
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* 08/02/01 brr Fixed debug statements in WaitOn functions.
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* 07/31/01 mmd Added SIMON_EnableInterrupts call.
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* 06/27/01 jke added to debug print statements. Changed logic of if state-
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* ments in IRQs to handle non-debug-execution
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* 06/21/01 jke added use of BSDIDRIVER and WakeUp macro, altered N8_dbgPrt
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* macro to encorporate "if (N8_IRQ_Debug_g)", making the
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* resulting source more readable and compact.
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* 06/12/01 jke altered to run under BSDi
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* 05/29/01 mmd Incorporated suggestions from code review.
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* 05/17/01 mmd Original version.
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****************************************************************************/
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/** @defgroup NSP2000Driver NSP2000 Device Driver
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*/
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#include "helper.h"
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#include "n8_driver_main.h"
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#include "n8_driver_api.h"
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#include "irq.h"
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#include "nsp2000_regs.h"
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#include "nsp_ioctl.h"
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#include "n8_OS_intf.h"
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#include "QMUtil.h"
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#include "n8_ea_common.h"
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#include "n8_pk_common.h"
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#include <sys/proc.h>
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/* FORWARD PROTOTYPES */
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void N8_PKHInterruptHandler ( NspInstance_t *NSPinstance_p,
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uint32_t reg_amba );
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void N8_RNHInterruptHandler ( NspInstance_t *NSPinstance_p );
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void N8_CCHInterruptHandler ( NspInstance_t *NSPinstance_p,
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uint32_t reg_amba );
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/* INSTANCE, INDEXED BY MINOR NUMBER */
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extern NspInstance_t NSPDeviceTable_g [DEF_MAX_SIMON_INSTANCES];
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/* NSPcount_g MAINTAINS THE NUMBER OF DETECTED HARDWARE INSTANCES */
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extern int NSPcount_g;
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extern wait_queue_head_t requestBlock;
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/* IRQ statistics */
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static int n8_IRQs_g = 0;
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static int n8_AMBA_IRQs_g = 0;
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static int n8_CCH_IRQs_g = 0;
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static int n8_PKH_IRQs_g = 0;
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int ambaTimerActive = FALSE;
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#define N8_RELOAD_AMBA_MASK (AMBAIRQ_PKP | AMBAIRQ_CCH | AMBAIRQ_RNG | \
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AMBAIRQ_Timer | AMBA_Timer_Reload)
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void cch_do_tasklet (unsigned long unused);
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#ifdef __linux
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DECLARE_TASKLET(cch_tasklet, cch_do_tasklet, 0);
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#endif
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void cch_do_tasklet (unsigned long unused)
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{
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int nspIdx;
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NSP2000REGS_t *nspRegPtr;
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NspInstance_t *localNSPinstance_p;
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int eaReqsComplete = 0;
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uint32_t cch_read;
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uint16_t newReadIndex;
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uint16_t cmdsComplete;
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/* The bridge timer interrupt is only enabled for the first */
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/* NSP, so when it fires, update the read pointer for each */
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/* device installed in the system. */
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for (nspIdx = 0; nspIdx < NSPcount_g; nspIdx++)
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{
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localNSPinstance_p = &NSPDeviceTable_g[nspIdx];
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nspRegPtr = (NSP2000REGS_t *)localNSPinstance_p->NSPregs_p;
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/* Read & store the read pointers on each timer interrupt. */
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cch_read = (nspRegPtr->cch_q_ptr>>16);
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/* Check for completed EA command blocks on */
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/* the AMBA timer interrupt */
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newReadIndex = cch_read;
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if (newReadIndex != localNSPinstance_p->EAreadIndex)
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{
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cmdsComplete = (newReadIndex - localNSPinstance_p->EAreadIndex) &
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(localNSPinstance_p->EAqueue_size-1);
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localNSPinstance_p->EAreadIndex = newReadIndex;
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eaReqsComplete += QMgrCheckQueue(N8_EA, nspIdx, cmdsComplete);
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}
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}
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/* Reload the AMBA timer only if there were */
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/* outstanding EA requests */
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if ((eaReqsComplete) || QMgrCount(N8_EA))
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{
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ambaTimerActive = TRUE;
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localNSPinstance_p = &NSPDeviceTable_g[N8_AMBA_TIMER_CHIP];
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nspRegPtr = (NSP2000REGS_t *)localNSPinstance_p->NSPregs_p;
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nspRegPtr->amba_pci_control = N8_RELOAD_AMBA_MASK;
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}
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if (eaReqsComplete)
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{
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WakeUp(&requestBlock);
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}
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}
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/*****************************************************************************
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* N8_MainInterruptHandler
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*****************************************************************************/
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/** @ingroup NSP2000Driver
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* @brief Main NSP2000 interrupt handler.
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*
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* This routine performs the main interrupt handling of the NSP2000.
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*
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* @param NSPinstance_p RO: Pointer to the information structure for an
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* NSP2000 hardware instance, containing a
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* pointer to its control register set.
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* @param debug RO: Specifies whether debug messages are enabled.
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*
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* @return
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* N/A
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*
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* @par Errors:
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* See return section for error information.
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*
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* @par Assumptions:
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* We are assuming that AMBA interrupts are used the same way in
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* each user process that might use them.
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*
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*****************************************************************************/
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#define DEF_NSP_IRQ_ACTIVE (AMBAIRQ_PKP | AMBAIRQ_CCH | AMBAIRQ_RNG | \
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AMBAIRQ_Bridge | AMBAIRQ_Timer)
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void n8_MainInterruptHandler(NspInstance_t *NSPinstance_p)
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{
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NSP2000REGS_t *nsp = (NSP2000REGS_t *)NSPinstance_p->NSPregs_p;
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uint32_t reg_amba = nsp->amba_pci_status;
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#ifdef __linux
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uint32_t temp;
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#endif
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/* CHECK FOR ACTIVE NSP2000 INTERRUPT */
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if (reg_amba & DEF_NSP_IRQ_ACTIVE)
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{
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/* Count the receipt of interrupt */
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#ifdef N8_IRQ_COUNT
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n8_IRQs_g++;
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#endif
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/* If this interrupt is from the Bridge Timer, reload it */
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if (reg_amba & AMBAIRQ_Timer)
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{
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/* Clear the AMBA timer interrupt */
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nsp->amba_pci_status = reg_amba;
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#ifdef N8_IRQ_COUNT
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n8_AMBA_IRQs_g++;
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#endif
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ambaTimerActive = FALSE;
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#ifdef __linux
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tasklet_schedule(&cch_tasklet);
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/* Ensure PCI write completes by reading register */
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/* before exiting the ISR. */
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temp = nsp->amba_pci_status;
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#else
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cch_do_tasklet(n8_IRQs_g);
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#endif
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}
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/* IF APPROPRIATE, RELEASE ANYONE BLOCKED ON AMBA INTERRUPTS */
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/* Note that usage of a single AMBAbitmask doesn't allow for */
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/* different processes to wait on different masks. However, */
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/* we only use the AMBA timer, and all processes that wait on */
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/* AMBA interrupts are just waiting on the timer. */
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if (NSPinstance_p->AMBAbitmask & reg_amba)
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{
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/* RELEASE BLOCKED CALL */
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/* We are using the timer of the AMBA to generate a */
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/* periodic interrupt. */
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WakeUp( &NSPinstance_p->AMBAblock );
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}
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/* HANDLE ANY RNG/PKE/EA INTERRUPTS */
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if (reg_amba & AMBAIRQ_PKP)
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{
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#ifdef N8_IRQ_COUNT
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n8_PKH_IRQs_g++;
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#endif
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N8_PKHInterruptHandler(NSPinstance_p, reg_amba);
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}
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if (reg_amba & AMBAIRQ_CCH)
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{
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#ifdef N8_IRQ_COUNT
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n8_CCH_IRQs_g++;
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#endif
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N8_CCHInterruptHandler(NSPinstance_p, reg_amba);
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}
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if (reg_amba & AMBAIRQ_RNG)
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{
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N8_RNHInterruptHandler(NSPinstance_p);
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}
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}
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return;
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}
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/*****************************************************************************
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* N8_PKHInterruptHandler
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*****************************************************************************/
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/** @ingroup NSP2000Driver
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* @brief PKH interrupt handler.
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*
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* This routine is called by the main interrupt handler to handle PKH
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* interrupts. It first samples the PKH control/status register for future
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* reference. It then clears all active bits, to handle all active interrupts.
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* If debug messages are enabled, it also translates the meaning of each
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* active bit.
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*
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* Bits 0-17 indicate PKH interrupts. An active bit is cleared by writing 1
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* to it.
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*
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* @param NSPinstance_p RO: Pointer to the information structure for an
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* NSP2000 hardware instance, containing a
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* pointer to its control register set.
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* @param reg_amba RO: Value reported in the AMBA Bridge Status Register
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*
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* @par Externals:
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* PKHIRQ_* RO: #define - Constants that identify each bit of the <BR>
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* PKH Control/Status register.
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*
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* @return
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* N/A
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*
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* @par Errors:
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* See return section for error information.
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*****************************************************************************/
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void N8_PKHInterruptHandler(NspInstance_t *NSPinstance_p,
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uint32_t reg_amba)
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{
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NSP2000REGS_t *nsp;
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unsigned long reg, newreg;
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uint16_t readIndx;
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uint16_t cmdsComplete;
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int reqsComplete = 0;
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nsp = (NSP2000REGS_t *)NSPinstance_p->NSPregs_p;
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/* Check for an error */
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if (reg_amba & AMBAPKH_Error)
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{
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/* An error has been detected, read and save PKH status register */
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reg = (unsigned long)nsp->pkh_control_status;
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NSPinstance_p->PKHirqstatus = reg;
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if (reg & PK_Status_Any_Error_Mask)
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{
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/* CLEAR PKH ENABLE TO ALLOW PKE TO STOP */
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nsp->pkh_control_status = 0;
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while (nsp->pkh_control_status & PK_Status_PKH_Busy)
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{
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/* WAITING FOR PKE_BUSY TO CLEAR */
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}
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/* CLEAR ALL SIGNALLING IRQS AND DISABLE PKH */
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newreg = reg & PK_Enable_All_Enable_Mask;
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/* If it is a problem with the command, call the QMgr to noop command blocks */
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if (reg & PK_Status_Cmd_Error_Mask)
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{
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NSPinstance_p->PKHcmderrors++;
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/* Read & store the current read pointer. */
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readIndx = nsp->pkh_q_ptr>>16;
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/* Check for completed PK command blocks */
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if (readIndx != NSPinstance_p->PKreadIndex)
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{
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cmdsComplete = (readIndx - NSPinstance_p->PKreadIndex) &
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(NSPinstance_p->PKqueue_size-1);
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NSPinstance_p->PKreadIndex = readIndx;
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/* Process any completed commands */
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reqsComplete = QMgrCheckQueue(N8_PKP, NSPinstance_p->chip,
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cmdsComplete);
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}
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/* Process the errored command */
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QMgrCmdError(N8_PKP, NSPinstance_p->chip, readIndx, reg);
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}
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/* Bus errors require no QMgr action, just update counter */
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else if (reg & PK_Status_Bus_Error_Mask)
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{
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NSPinstance_p->PKHbuserrors++;
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}
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/* update register & reenable the PKH */
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nsp->pkh_control_status = newreg | PK_Status_PKH_Enable;
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/* IF APPROPRIATE, RELEASE ANYONE BLOCKED ON PKH INTERRUPTS */
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if (NSPinstance_p->PKHbitmask & reg)
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{
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/* RELEASE BLOCKED CALL */
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WakeUp(&(NSPinstance_p->PKHblock));
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|
|
/* PREVENT REENTRY OF THE BLOCKING FUNCTIONALITY */
|
|
NSPinstance_p->PKHbitmask = 0;
|
|
}
|
|
}
|
|
}
|
|
else /* No Errors, this is a command complete interrupt */
|
|
{
|
|
/* Clear the command complete bit */
|
|
nsp->pkh_control_status = PK_Enable_PKH_Enable |
|
|
PK_Enable_Cmd_Complete_Enable;
|
|
|
|
/* Read & store the current read pointer. */
|
|
readIndx = nsp->pkh_q_ptr>>16;
|
|
|
|
/* Process the completed PK command blocks */
|
|
cmdsComplete = (readIndx - NSPinstance_p->PKreadIndex) &
|
|
(NSPinstance_p->PKqueue_size-1);
|
|
NSPinstance_p->PKreadIndex = readIndx;
|
|
reqsComplete = QMgrCheckQueue(N8_PKP, NSPinstance_p->chip, cmdsComplete);
|
|
|
|
}
|
|
if (reqsComplete)
|
|
{
|
|
WakeUp(&requestBlock);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
* N8_RNHInterruptHandler
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief RNH interrupt handler.
|
|
*
|
|
* This routine is called by the main interrupt handler to handle RNH
|
|
* interrupts. It first samples the RNH control/status register for future
|
|
* reference. It then clears all active bits, to handle all active interrupts.
|
|
* If debug messages are enabled, it also translates the meaning of each
|
|
* active bit.
|
|
*
|
|
* Bits 20-23 indicate RNH interrupts. An active bit is cleared by writing 1
|
|
* to it.
|
|
*
|
|
* @param NSPinstance_p RO: Pointer to the information structure for an
|
|
* NSP2000 hardware instance, containing a
|
|
* pointer to its control register set.
|
|
*
|
|
* @par Externals:
|
|
* RNHIRQ_* RO: #define - Constants that identify each bit of the <BR>
|
|
* RNH Control/Status register.
|
|
*
|
|
* @return
|
|
* N/A
|
|
*
|
|
* @par Errors:
|
|
* See return section for error information.
|
|
*****************************************************************************/
|
|
|
|
void N8_RNHInterruptHandler(NspInstance_t *NSPinstance_p)
|
|
{
|
|
NSP2000REGS_t *nsp;
|
|
unsigned long reg, newreg;
|
|
unsigned char reenable = 1;
|
|
|
|
/* READ AND SAVE RNH STATUS REGISTER */
|
|
nsp = (NSP2000REGS_t *)NSPinstance_p->NSPregs_p;
|
|
reg = (unsigned long)nsp->rnh_control_status;
|
|
NSPinstance_p->RNHirqstatus = reg;
|
|
|
|
/* CLEAR RNH ENABLE TO ALLOW RNG TO STOP */
|
|
nsp->rnh_control_status = 0;
|
|
while (nsp->rnh_control_status & RNH_Status_Transfer_Busy)
|
|
{
|
|
/* WAITING FOR XFER_BUSY TO CLEAR */
|
|
}
|
|
|
|
/* CLEAR ALL SIGNALLING IRQS AND RE-ENABLE RNH */
|
|
newreg = reg & RNH_Status_Any_Condition_Mask;
|
|
|
|
/* DISABLE RNH IF BIG ERROR */
|
|
if (reg & DEF_RNH_BIGERROR_IRQ_BITS)
|
|
{
|
|
/* IRQPRINT(("NSP2000: Serious error - RNG execution halted.\n")); */
|
|
reenable = 0;
|
|
}
|
|
|
|
/* Record the bus error */
|
|
else if (reg & RNH_Status_Bus_Error)
|
|
{
|
|
NSPinstance_p->RNHbuserrors++;
|
|
}
|
|
|
|
/* UPDATE REGISTER */
|
|
nsp->rnh_control_status = newreg;
|
|
if (reenable)
|
|
{
|
|
nsp->rnh_control_status = RNH_Status_Transfer_Enable;
|
|
}
|
|
|
|
/* IF APPROPRIATE, RELEASE ANYONE BLOCKED ON RNH INTERRUPTS */
|
|
if (NSPinstance_p->RNHbitmask & reg)
|
|
{
|
|
/* RELEASE BLOCKED CALL */
|
|
WakeUp(&(NSPinstance_p->RNHblock));
|
|
|
|
/* PREVENT REENTRY OF THE BLOCKING FUNCTIONALITY */
|
|
NSPinstance_p->RNHbitmask = 0;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
* N8_CCHInterruptHandler
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief CCH interrupt handler.
|
|
*
|
|
* This routine is called by the main interrupt handler to handle CCH
|
|
* interrupts. It first samples the CCH control/status register for future
|
|
* reference. It then clears all active bits, to handle all active interrupts.
|
|
* If debug messages are enabled, it also translates the meaning of each
|
|
* active bit.
|
|
*
|
|
* Bits 0-15 indicate CCH interrupts. An active bit is cleared by writing 1
|
|
* to it.
|
|
*
|
|
* @param NSPinstance_p RO: Pointer to the information structure for an
|
|
* NSP2000 hardware instance, containing a
|
|
* pointer to its control register set.
|
|
* @param reg_amba RO: Value reported in the AMBA Bridge Status Register
|
|
*
|
|
* @par Externals:
|
|
* CCHIRQ_* RO: #define - Constants that identify each bit of the <BR>
|
|
* CCH Control/Status register.
|
|
*
|
|
* @return
|
|
* N/A
|
|
*
|
|
* @par Errors:
|
|
* See return section for error information.
|
|
*****************************************************************************/
|
|
|
|
void N8_CCHInterruptHandler(NspInstance_t *NSPinstance_p,
|
|
uint32_t reg_amba)
|
|
{
|
|
NSP2000REGS_t *nsp;
|
|
unsigned long reg;
|
|
uint16_t readIndx;
|
|
uint16_t cmdsComplete;
|
|
|
|
nsp = (NSP2000REGS_t *)NSPinstance_p->NSPregs_p;
|
|
|
|
/* Check for an error */
|
|
if (reg_amba & AMBACCH_Error)
|
|
{
|
|
/* An error has been detected, read and save CCH status register */
|
|
reg = (unsigned long)nsp->cch_control_status;
|
|
NSPinstance_p->CCHirqstatus = reg;
|
|
|
|
if (reg & EA_Status_Any_Error_Mask)
|
|
{
|
|
/* CLEAR CCH ENABLE TO ALLOW CC TO STOP */
|
|
nsp->cch_control_status = 0;
|
|
while (nsp->cch_control_status & EA_Status_Module_Busy)
|
|
{
|
|
/* WAITING FOR CCH_BUSY TO CLEAR */
|
|
}
|
|
|
|
/* Clear all outstanding IRQS */
|
|
nsp->cch_control_status = reg & EA_Status_Any_Condition_Mask;
|
|
|
|
/* If it is a problem with the command, call the QMgr to noop command blocks */
|
|
if (reg & EA_Status_Cmd_Error_Mask)
|
|
{
|
|
NSPinstance_p->CCHcmderrors++;
|
|
/* Read & store the current read pointer. */
|
|
readIndx = nsp->cch_q_ptr >> 16;
|
|
|
|
/* Check for completed EA command blocks */
|
|
if (readIndx != NSPinstance_p->EAreadIndex)
|
|
{
|
|
cmdsComplete = (readIndx - NSPinstance_p->EAreadIndex) &
|
|
(NSPinstance_p->EAqueue_size-1);
|
|
NSPinstance_p->EAreadIndex = readIndx;
|
|
/* Process any completed commands */
|
|
QMgrCheckQueue(N8_EA, NSPinstance_p->chip, cmdsComplete);
|
|
}
|
|
|
|
/* Process the errored command */
|
|
QMgrCmdError(N8_EA, NSPinstance_p->chip, readIndx, reg);
|
|
}
|
|
|
|
/* Bus errors require no QMgr action, just update counter */
|
|
else if (reg & EA_Status_Bus_Error_Mask)
|
|
{
|
|
NSPinstance_p->CCHbuserrors++;
|
|
}
|
|
|
|
/* Reenable the CCH */
|
|
nsp->cch_control_status = EA_Enable_Module_Enable;
|
|
|
|
/* IF APPROPRIATE, RELEASE ANYONE BLOCKED ON CCH INTERRUPTS */
|
|
if (NSPinstance_p->CCHbitmask & reg)
|
|
{
|
|
/* RELEASE BLOCKED CALL */
|
|
WakeUp(&(NSPinstance_p->CCHblock));
|
|
|
|
/* PREVENT REENTRY OF THE BLOCKING FUNCTIONALITY */
|
|
NSPinstance_p->CCHbitmask = 0;
|
|
}
|
|
}
|
|
}
|
|
else /* No Errors, this is a command complete interrupt */
|
|
{
|
|
/* Clear the command complete bit */
|
|
nsp->cch_control_status = EA_Enable_Module_Enable |
|
|
EA_Enable_Cmd_Complete_Enable;
|
|
|
|
/* Read & store the current read pointer. */
|
|
readIndx = nsp->cch_q_ptr >> 16;
|
|
|
|
/* Process the completed EA command blocks */
|
|
cmdsComplete = (readIndx - NSPinstance_p->EAreadIndex) &
|
|
(NSPinstance_p->EAqueue_size-1);
|
|
NSPinstance_p->EAreadIndex = readIndx;
|
|
QMgrCheckQueue(N8_EA, NSPinstance_p->chip, cmdsComplete);
|
|
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
* waitOnInterrupt
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief Interrupt notification routine.
|
|
*
|
|
* This routine allows a process to block for interrupt notification for the
|
|
* PKE, EA, RNG, or AMBA. This routine initializes a wait queue and blocks on
|
|
* it with a timeout value. If the specified execution core signals an IRQ that
|
|
* matches one of the set bits in the bitmask, the IRQ handler will release
|
|
* this blocked process for completion. Otherwise, if no satisfactory IRQ is
|
|
* received, this routine will time out and return with appropriate error code.
|
|
*
|
|
* @param NSPinstance_p RO: Pointer to the information structure for an
|
|
* NSP2000 hardware instance, containing a
|
|
* pointer to its control register set.
|
|
* @param bitmask RO: Bitmask to filter received interrupts.
|
|
* @param coretype RO: Specifies which execution core to monitor.
|
|
* @param timeout RO: Timeout value for blocking, in seconds.
|
|
* @param debug RO: Specifies whether debug messages are enabled.
|
|
* @param interruptable RO: Specifies whether the wait should be interruptable
|
|
*
|
|
* @par Externals:
|
|
* N8_DAPI_* RO: #define - Constants to specify an execution core.
|
|
*
|
|
* @return
|
|
* -EINVAL Invalid core specified.
|
|
* 0 Timeout - interrupt not received.
|
|
* 1 Success - interrupt received.
|
|
*
|
|
* @par Errors:
|
|
* See return section for error information.
|
|
*****************************************************************************/
|
|
|
|
int waitOnInterrupt ( N8_Unit_t chip,
|
|
unsigned char coretype,
|
|
unsigned long bitmask,
|
|
unsigned long timeout,
|
|
int interruptable )
|
|
{
|
|
unsigned char rc;
|
|
unsigned char debug = 0; /* was passed from DEBUG_IRQ in nsp_ioctl.c */
|
|
NspInstance_t *NSPinstance_p = &NSPDeviceTable_g[chip];
|
|
|
|
if (interruptable == FALSE)
|
|
{
|
|
if (coretype == N8_DAPI_AMBA)
|
|
{
|
|
NSPinstance_p->AMBAbitmask = bitmask;
|
|
return 1;
|
|
}
|
|
else
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
if (coretype == N8_DAPI_PKE)
|
|
{
|
|
NSPinstance_p->PKHbitmask = bitmask;
|
|
rc = N8_BlockWithTimeout(&(NSPinstance_p->PKHblock),
|
|
timeout, debug);
|
|
}
|
|
else if (coretype == N8_DAPI_RNG)
|
|
{
|
|
NSPinstance_p->RNHbitmask = bitmask;
|
|
rc = N8_BlockWithTimeout(&(NSPinstance_p->RNHblock),
|
|
timeout, debug);
|
|
}
|
|
else if (coretype == N8_DAPI_EA)
|
|
{
|
|
NSPinstance_p->CCHbitmask = bitmask;
|
|
rc = N8_BlockWithTimeout(&(NSPinstance_p->CCHblock),
|
|
timeout, debug);
|
|
}
|
|
else if (coretype == N8_DAPI_AMBA)
|
|
{
|
|
NSPinstance_p->AMBAbitmask = bitmask;
|
|
|
|
/* We are using the timer of the AMBA to generate a */
|
|
/* periodic interrupt. */
|
|
rc = N8_BlockWithTimeout(
|
|
&(NSPinstance_p->AMBAblock),
|
|
timeout,
|
|
debug);
|
|
|
|
/* Note that the AMBAbitmask will not be cleared. */
|
|
/* There is no hard (other than some amount of overhead) */
|
|
/* of doing extra wake-ups. If we do clear the bitmask */
|
|
/* then it would need to be on a per process basis, */
|
|
/* because otherwise, one process could starting to do a */
|
|
/* block, while the other is doing a clear. Then the */
|
|
/* wake up will never occur, as the bitmask is 0. */
|
|
/* NSPinstance_p->AMBAbitmask = 0; */
|
|
|
|
/* The advance to the next wait block occurs in the isr. */
|
|
|
|
}
|
|
else
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
* n8_WaitOnInterrupt
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief Interrupt notification routine.
|
|
*
|
|
* This routine allows a process to block for interrupt notification for the
|
|
* PKE, EA, RNG, or AMBA. This routine initializes a wait queue and blocks on
|
|
* it with a timeout value. If the specified execution core signals an IRQ that
|
|
* matches one of the set bits in the bitmask, the IRQ handler will release
|
|
* this blocked process for completion. Otherwise, if no satisfactory IRQ is
|
|
* received, this routine will time out and return with appropriate error code.
|
|
*
|
|
* @param NSPinstance_p RO: Pointer to the information structure for an
|
|
* NSP2000 hardware instance, containing a
|
|
* pointer to its control register set.
|
|
* @param bitmask RO: Bitmask to filter received interrupts.
|
|
* @param coretype RO: Specifies which execution core to monitor.
|
|
* @param timeout RO: Timeout value for blocking, in seconds.
|
|
* @param debug RO: Specifies whether debug messages are enabled.
|
|
*
|
|
* @par Externals:
|
|
* N8_DAPI_* RO: #define - Constants to specify an execution core.
|
|
*
|
|
* @return
|
|
* -EINVAL Invalid core specified.
|
|
* 0 Timeout - interrupt not received.
|
|
* 1 Success - interrupt received.
|
|
*
|
|
* @par Errors:
|
|
* See return section for error information.
|
|
*****************************************************************************/
|
|
|
|
N8_Status_t N8_WaitOnInterrupt ( N8_Unit_t chip,
|
|
unsigned char coretype,
|
|
unsigned long bitmask,
|
|
unsigned long timeout )
|
|
{
|
|
return waitOnInterrupt(chip, coretype, bitmask, timeout, FALSE);
|
|
}
|
|
|
|
|
|
N8_Status_t N8_WaitOnRequest ( int timeout )
|
|
{
|
|
|
|
if (N8_BlockWithTimeout(&requestBlock, timeout, 0))
|
|
{
|
|
return (N8_STATUS_OK);
|
|
}
|
|
return (N8_TIMEOUT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
* reload_AMBA_timer
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief This function reloads the AMBA timer.
|
|
*
|
|
* @return
|
|
* N/A
|
|
*
|
|
* @par Errors:
|
|
* N/A
|
|
*****************************************************************************/
|
|
void reload_AMBA_timer(void)
|
|
{
|
|
NspInstance_t *NSPinstance_p;
|
|
NSP2000REGS_t *nspRegPtr;
|
|
|
|
if (ambaTimerActive == FALSE)
|
|
{
|
|
NSPinstance_p = &NSPDeviceTable_g[N8_AMBA_TIMER_CHIP];
|
|
nspRegPtr = (NSP2000REGS_t *)NSPinstance_p->NSPregs_p;
|
|
ambaTimerActive = TRUE;
|
|
nspRegPtr->amba_pci_control = N8_RELOAD_AMBA_MASK;
|
|
}
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* n8_DisplayIRQ
|
|
*****************************************************************************/
|
|
/** @ingroup NSP2000Driver
|
|
* @brief Displays the IRQ statistics
|
|
*
|
|
* This routine displays the NSP2000's IRQ statistics to the
|
|
* kernel log. This routine is intended for debugging purposes.
|
|
*
|
|
* @return
|
|
* N/A
|
|
*
|
|
* @par Errors:
|
|
* See return section for error information.
|
|
*****************************************************************************/
|
|
void n8_DisplayIRQ(void)
|
|
{
|
|
int nspIdx;
|
|
NspInstance_t *NSPinstance_p;
|
|
|
|
N8_PRINT(KERN_CRIT "\n");
|
|
N8_PRINT(KERN_CRIT "NSP2000: Displaying IRQ statistics:\n\n");
|
|
|
|
N8_PRINT(KERN_CRIT " AMBA IRQ's = %d\n", n8_AMBA_IRQs_g);
|
|
N8_PRINT(KERN_CRIT " CCH IRQ's = %d\n", n8_CCH_IRQs_g);
|
|
N8_PRINT(KERN_CRIT " PKH IRQ's = %d\n", n8_PKH_IRQs_g);
|
|
N8_PRINT(KERN_CRIT " Total IRQ's = %d\n", n8_IRQs_g);
|
|
|
|
for (nspIdx = 0; nspIdx < NSPcount_g; nspIdx++)
|
|
{
|
|
NSPinstance_p = &NSPDeviceTable_g[nspIdx];
|
|
|
|
N8_PRINT(KERN_CRIT "\n");
|
|
N8_PRINT(KERN_CRIT "NSP2000: Displaying IRQ statistics for chip %d:\n",
|
|
NSPinstance_p->chip);
|
|
N8_PRINT(KERN_CRIT " CCH Bus errors = %d\n", NSPinstance_p->CCHbuserrors);
|
|
N8_PRINT(KERN_CRIT " PKH Bus errors = %d\n", NSPinstance_p->PKHbuserrors);
|
|
N8_PRINT(KERN_CRIT " CCH Cmd errors = %d\n", NSPinstance_p->CCHcmderrors);
|
|
N8_PRINT(KERN_CRIT " PKH Cmd errors = %d\n", NSPinstance_p->PKHcmderrors);
|
|
}
|
|
}
|
|
|