e627b7fefc
accept ranges as well as single addresses. Still need to go through any key areas and remove the malloc's and replace these with some sort of pooling instead.
401 lines
12 KiB
C++
401 lines
12 KiB
C++
/* $NetBSD: fwohcivar.h,v 1.20 2002/12/13 07:47:53 jmc Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of the 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IEEE1394_FWOHCIVAR_H_
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#define _DEV_IEEE1394_FWOHCIVAR_H_
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#include <sys/callout.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#define OHCI_PAGE_SIZE 0x0800
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#define OHCI_BUF_ARRQ_CNT 16
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#define OHCI_BUF_ARRS_CNT 8
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#define OHCI_BUF_ATRQ_CNT (8*8)
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#define OHCI_BUF_ATRS_CNT (8*8)
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#define OHCI_BUF_IR_CNT 8
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#define OHCI_BUF_CNT \
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(OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + OHCI_BUF_ATRQ_CNT + \
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OHCI_BUF_ATRS_CNT + OHCI_BUF_IR_CNT + 1 + 1)
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#define OHCI_LOOP 1000
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#define OHCI_SELFID_TIMEOUT (hz * 3)
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#define OHCI_ASYNC_STREAM 0x100
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struct fwohci_softc;
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struct fwohci_pkt;
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struct mbuf;
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struct fwohci_buf {
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TAILQ_ENTRY(fwohci_buf) fb_list;
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bus_dma_segment_t fb_seg;
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int fb_nseg;
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bus_dmamap_t fb_dmamap; /* DMA map of the buffer */
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caddr_t fb_buf; /* kernel virtual addr of the buffer */
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struct fwohci_desc *fb_desc; /* kernel virtual addr of descriptor */
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bus_addr_t fb_daddr; /* physical addr of the descriptor */
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int fb_off;
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struct mbuf *fb_m;
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void *fb_statusarg;
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void (*fb_callback)(struct device *, struct mbuf *);
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int (*fb_statuscb)(struct fwohci_softc *, void *, struct fwohci_pkt *);
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};
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struct fwohci_pkt {
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int fp_tcode;
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int fp_hlen;
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int fp_dlen;
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u_int32_t fp_hdr[4];
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struct uio fp_uio;
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struct iovec fp_iov[6];
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u_int32_t *fp_trail;
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struct mbuf *fp_m;
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u_int16_t fp_status;
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void *fp_statusarg;
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int (*fp_statuscb)(struct fwohci_softc *, void *, struct fwohci_pkt *);
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void (*fp_callback)(struct device *, struct mbuf *);
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};
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struct fwohci_handler {
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LIST_ENTRY(fwohci_handler) fh_list;
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u_int32_t fh_tcode; /* ARRQ / ARRS / IR */
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u_int32_t fh_key1; /* addrhi / srcid / chan */
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u_int32_t fh_key2; /* addrlo / tlabel / tag */
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u_int32_t fh_key3; /* for addr's a possible range. */
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int (*fh_handler)(struct fwohci_softc *, void *,
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struct fwohci_pkt *);
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void *fh_handarg;
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};
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struct fwohci_ctx {
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int fc_ctx;
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int fc_type; /* FWOHCI_CTX_(ASYNC|ISO_SINGLE|ISO_MULTI) */
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int fc_bufcnt;
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u_int32_t *fc_branch;
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TAILQ_HEAD(fwohci_buf_s, fwohci_buf) fc_buf;
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struct fwohci_buf_s fc_buf2; /* for iso */
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LIST_HEAD(, fwohci_handler) fc_handler;
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struct fwohci_buf *fc_buffers;
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};
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struct fwohci_ir_ctx {
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struct fwohci_softc *irc_sc;
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int irc_num; /* context number */
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int irc_flags; /* IEEE1394_IR_* */
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int irc_status;
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#define IRC_STATUS_READY 0x0001
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#define IRC_STATUS_RUN 0x0002
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#define IRC_STATUS_SLEEPING 0x0004
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#define IRC_STATUS_RECEIVE 0x0008
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int irc_pktcount;
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int irc_channel; /* channel number */
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int irc_tagbm; /* tag bitmap */
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int irc_maxsize; /* maxmum data size for a packet */
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int irc_maxqueuelen; /* for debug purpose */
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int irc_maxqueuepos;
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struct fwohci_desc *irc_readtop; /* where data start */
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struct fwohci_desc *irc_writeend; /* where branch addr is 0 */
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u_int32_t irc_savedbranch;
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struct fwohci_iso_buf *irc_buf_ptr;
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/* data for descriptor */
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bus_dma_segment_t irc_desc_seg;
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bus_dmamap_t irc_desc_dmamap;
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int irc_desc_num; /* number of descriptors */
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int irc_desc_size; /* actual size in byte */
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struct fwohci_desc *irc_desc_map; /* Do not change */
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int irc_desc_nsegs;
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volatile void *irc_waitchan; /* wait channel */
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struct selinfo irc_sel;
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/* data for buffer */
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bus_dma_segment_t irc_buf_segs[16];
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bus_dmamap_t irc_buf_dmamap;
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int irc_buf_totalsize;
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int irc_buf_nsegs;
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u_int8_t *irc_buf;
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/* for debug purpose */
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#ifdef FWOHCI_WAIT_DEBUG
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u_int16_t irc_cycle[3]; /* 0 for wait time, 1 for intr time */
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#endif
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};
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/*
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* Context dedicated for isochronous transmit. Two data structure are
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* defined.
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*/
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struct fwohci_it_ctx;
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#define IEEE1394_IT_PKTHDR 0x0001
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struct fwohci_it_dmabuf {
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struct fwohci_it_ctx *itd_ctx;
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int itd_num;
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int itd_flags;
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#define ITD_FLAGS_LOCK 0x0001
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#define ITD_FLAGS_UNLOCK 0x0000
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#define ITD_FLAGS_LOCK_MASK 0x0001
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/* memory for descriptor */
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struct fwohci_desc *itd_desc; /* top of descriptor */
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bus_addr_t itd_desc_phys; /* physical addr of 1st descriptor */
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int itd_descsize; /* number of total descriptors */
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struct fwohci_desc *itd_lastdesc; /* last valid descriptor */
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int itd_maxpacket; /* maximum packets for the buffer */
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int itd_npacket; /* number of valid packets */
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int itd_maxsize; /* maximum packet size */
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/* DMA buffer */
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#define FWOHCI_MAX_ITDATASEG 8
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bus_dma_segment_t itd_seg[FWOHCI_MAX_ITDATASEG];
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bus_dmamap_t itd_dmamap;
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int itd_size; /* count in byte */
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u_int8_t *itd_buf;
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int itd_nsegs;
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/* header store descriptor */
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struct fwohci_desc *itd_store;
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bus_addr_t itd_store_phys;
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u_int32_t itd_savedbranch;
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#if 0
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int fwohci_itd_construct(struct fwohci_it_ctx *, struct fwohci_it_dmabuf *, int no, struct fwohci_desc *desc, int descsize, int maxsize, paddr_t scratch);
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void fwohci_itd_destruct(struct fwohci_it_dmabuf *);
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int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int ndata,
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struct ieee1394_it_datalist *);
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int fwohci_itd_link(struct fwohci_it_dmabuf *, struct fwohci_it_dmabuf *);
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bus_addr_t fwohci_itd_list_head(struct fwohci_it_dmabuf *);
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void fwohci_itd_clean(struct fwohci_it_dmabuf *);
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int fwohci_itd_isfilled(struct fwohci_it_dmabuf *);
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int fwohci_itd_hasdata(struct fwohci_it_dmabuf *);
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int fwohci_itd_isfull(struct fwohci_it_dmabuf *);
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#endif
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#define fwohci_itd_list_head(itd) (itd)->itd_desc_phys
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#define fwohci_itd_hasdata(itd) (itd)->itd_npacket
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#define fwohci_itd_isfull(itd) \
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((itd)->itd_npacket == (itd)->itd_maxpacket)
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#define fwohci_itd_islocked(itd) \
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((itd)->itd_flags & ITD_FLAGS_LOCK)
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};
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struct fwohci_it_ctx {
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struct fwohci_softc *itc_sc;
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int itc_num; /* context number */
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volatile int itc_flags; /* flags */
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#define ITC_FLAGS_RUN 0x0001
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int itc_channel; /* channel number */
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int itc_tag; /* tag */
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int itc_maxsize; /* maxmum data size for a packet */
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int itc_speed; /* speed */
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struct fwohci_it_dmabuf *itc_buf; /* array for fwohci_it_dmabuf */
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int itc_bufnum; /* const: num of elements in itc_buf array */
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#if 1
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volatile struct fwohci_it_dmabuf *itc_buf_start;
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struct fwohci_it_dmabuf *itc_buf_end;
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struct fwohci_it_dmabuf *itc_buf_linkend;
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#endif
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volatile int16_t itc_buf_cnt; /* # buffers which contain data */
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#if 0
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int16_t itc_bufidx_start;
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int16_t itc_bufidx_end;
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int16_t itc_bufidx_linkend;
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#endif
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/* data for descriptor */
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bus_dma_segment_t itc_dseg;
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bus_dmamap_t itc_ddmamap;
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int itc_descsize; /* count in byte */
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u_int8_t *itc_descmap;
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int itc_dnsegs;
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volatile u_int32_t *itc_scratch; /* descriptor decoder will write */
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u_int32_t itc_scratch_paddr;
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volatile void *itc_waitchan; /* wait channel */
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int itc_outpkt; /* only for debugging */
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#if 0
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struct fwohci_it_ctx *fwohci_it_ctx_construct(int);
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void fwohci_it_ctx_destruct(struct fwohci_it_ctx *);
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void fwohci_it_ctx_intr(struct fwohci_it_ctx *);
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int fwohci_it_ctx_writedata(ieee1394_it_tag_t, int ndata,
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struct ieee1394_it_datalist *);
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private:
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void fwohci_it_ctx_run(struct fwohci_it_ctx *itc);
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void fwohci_it_intr(struct fwohci_softc *, struct fwohci_it_ctx *);
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#endif
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#define INC_BUF(itc, buf) \
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do { \
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if (++buf == (itc)->itc_buf + (itc)->itc_bufnum) { \
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buf = &(itc)->itc_buf[0]; \
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} \
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} while (0)
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};
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struct fwohci_uidtbl {
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int fu_valid;
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u_int8_t fu_uid[8];
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};
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/*
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* Needed to keep track of outstanding packets during a read op. Since the
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* packet stream is asynch it's possible to parse a response packet before the
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* ack bits are processed. In this case something needs to track whether the
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* abuf is still valid before possibly attempting to use items from within it.
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*/
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struct fwohci_cb {
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struct ieee1394_abuf *ab;
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int count;
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int abuf_valid;
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};
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struct fwohci_softc {
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struct ieee1394_softc sc_sc1394;
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struct evcnt sc_intrcnt;
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struct evcnt sc_isocnt;
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struct evcnt sc_ascnt;
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struct evcnt sc_itintrcnt;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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bus_dma_tag_t sc_dmat;
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bus_size_t sc_memsize;
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#if 0
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/* Mandatory structures to get the link enabled
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*/
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bus_dmamap_t sc_configrom_map;
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bus_dmamap_t sc_selfid_map;
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u_int32_t *sc_selfid_buf;
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u_int32_t *sc_configrom;
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#endif
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bus_dma_segment_t sc_dseg;
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int sc_dnseg;
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bus_dmamap_t sc_ddmamap;
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struct fwohci_desc *sc_desc;
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u_int8_t *sc_descmap;
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int sc_descsize;
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int sc_isoctx;
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int sc_itctx;
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void *sc_shutdownhook;
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void *sc_powerhook;
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struct callout sc_selfid_callout;
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int sc_selfid_fail;
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struct fwohci_ctx *sc_ctx_arrq;
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struct fwohci_ctx *sc_ctx_arrs;
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struct fwohci_ctx *sc_ctx_atrq;
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struct fwohci_ctx *sc_ctx_atrs;
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struct fwohci_ctx **sc_ctx_as; /* previously sc_ctx_ir */
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struct fwohci_buf sc_buf_cnfrom;
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struct fwohci_buf sc_buf_selfid;
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struct fwohci_ir_ctx **sc_ctx_ir;
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struct fwohci_it_ctx **sc_ctx_it;
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struct proc *sc_event_thread;
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int sc_dying;
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u_int32_t sc_intmask;
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u_int32_t sc_iso;
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u_int8_t sc_csr[CSR_SB_END];
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struct fwohci_uidtbl *sc_uidtbl;
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u_int16_t sc_nodeid; /* Full Node ID of this node */
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u_int8_t sc_rootid; /* Phy ID of Root */
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u_int8_t sc_irmid; /* Phy ID of IRM */
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u_int8_t sc_tlabel; /* Transaction Label */
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LIST_HEAD(, ieee1394_softc) sc_nodelist;
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};
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int fwohci_init (struct fwohci_softc *, const struct evcnt *);
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int fwohci_intr (void *);
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int fwohci_print (void *, const char *);
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int fwohci_detach(struct fwohci_softc *, int);
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int fwohci_activate(struct device *, enum devact);
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/* Macros to read and write the OHCI registers
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*/
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#define OHCI_CSR_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, htole32(val))
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#define OHCI_CSR_READ(sc, reg) \
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le32toh(bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, reg))
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#define FWOHCI_CTX_ASYNC 0
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#define FWOHCI_CTX_ISO_SINGLE 1 /* for async stream */
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#define FWOHCI_CTX_ISO_MULTI 2 /* for isochronous */
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/* Locators. */
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#include "locators.h"
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#define fwbuscf_idhi cf_loc[FWBUSCF_IDHI]
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#define FWBUS_UNK_IDHI FWBUSCF_IDHI_DEFAULT
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#define fwbuscf_idlo cf_loc[FWBUSCF_IDLO]
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#define FWBUS_UNK_IDLO FWBUSCF_IDLO_DEFAULT
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#endif /* _DEV_IEEE1394_FWOHCIVAR_H_ */
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