216b9b2ea6
- Steer i80200 PMU and BCU interrupts to IRQ# (for lack of a better place, at the moment). - Disable all interrupts other than external-IRQ# in the i80200 ICU; we don't deal with any of the others, yet.
290 lines
7.2 KiB
C
290 lines
7.2 KiB
C
/* $NetBSD: iq80310_intr.c,v 1.6 2001/12/01 06:15:36 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Interrupt support for the Intel IQ80310.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/cpu.h>
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#include <arm/cpufunc.h>
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#include <arm/xscale/i80200reg.h>
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#include <evbarm/iq80310/iq80310reg.h>
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#include <evbarm/iq80310/iq80310var.h>
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#include <evbarm/iq80310/obiovar.h>
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irqhandler_t *irqhandlers[NIRQS];
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int current_intr_depth; /* Depth of interrupt nesting */
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u_int intr_claimed_mask; /* Interrupts that are claimed */
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u_int intr_disabled_mask; /* Interrupts that are temporarily disabled */
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u_int intr_current_mask; /* Interrupts currently allowable */
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u_int spl_mask;
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u_int irqmasks[IPL_LEVELS];
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u_int irqblock[NIRQS];
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u_int iq80310_intrmask; /* actual interrupts currently enabled */
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extern u_int soft_interrupts; /* Only so we can initialise it */
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extern char *_intrnames;
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extern void set_spl_masks(void);
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/* Called only from assembler code. */
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uint32_t iq80310_intstat_read(void);
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void stray_irqhandler(int);
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/*
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* We have 8 interrupt source bits -- 5 in the XINT3 register, and 3
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* in the XINT0 register (the upper 3).
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*/
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#define IRQ_BITS 0xff
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void
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irq_init(void)
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{
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int loop;
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/* Clear all the IRQ handlers and the IRQ block masks. */
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for (loop = 0; loop < NIRQS; ++loop) {
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irqhandlers[loop] = NULL;
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irqblock[loop] = 0;
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}
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/*
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* Set up the irqmasks for the different interrupt priority
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* levels. We will start with no bits set and these will be
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* updated as handlers are installed at different IPLs.
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*/
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for (loop = 0; loop < IPL_LEVELS; ++loop)
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irqmasks[loop] = 0;
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current_intr_depth = 0;
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intr_claimed_mask = 0x00000000;
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intr_disabled_mask = 0x00000000;
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intr_current_mask = 0x00000000;
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spl_mask = 0x00000000;
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soft_interrupts = 0x00000000;
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set_spl_masks();
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irq_setmasks();
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/* Steer PMU and BCU interrupts to IRQ. */
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__asm __volatile("mcr p13, 0, %0, c2, c0, 0"
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:
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: "r" (0));
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/*
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* Enable external IRQs, disable external FIQs and
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* the PMU and BCU interrupts.
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*/
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__asm __volatile("mcr p13, 0, %0, c0, c0, 0"
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:
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: "r" (INTCTL_IM));
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/* Enable IRQs. */
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enable_interrupts(I32_bit);
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}
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uint32_t
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iq80310_intstat_read(void)
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{
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uint32_t intstat;
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intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f;
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if (1/*rev F or later board*/)
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intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5;
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/*
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* Yuck. Even if the interrupt is disabled, the bit will
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* still light up in the interrupt status register (it
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* just won't assert IRQ#).
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*/
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return (intstat & iq80310_intrmask);
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}
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__inline void
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irq_setmasks_nointr(void)
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{
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u_int disabled;
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/* The actual mask of IRQs actually right *right now*. */
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iq80310_intrmask = (intr_current_mask & spl_mask) & IRQ_BITS;
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/*
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* The XINT_MASK register sets a bit to *disable*.
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*/
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disabled = ~iq80310_intrmask;
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/*
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* The PCI interrupts are all masked by a single
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* bit in XINT3.
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*/
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if (disabled >> 5)
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disabled |= XINT3_SINTD;
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CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f);
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}
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void
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irq_setmasks(void)
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{
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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irq_setmasks_nointr();
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restore_interrupts(oldirqstate);
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}
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void
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enable_irq(int irq)
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{
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intr_claimed_mask |= (1U << irq);
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intr_current_mask = intr_claimed_mask & ~intr_disabled_mask;
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irq_setmasks_nointr();
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}
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void
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disable_irq(int irq)
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{
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intr_claimed_mask &= ~(1U << irq);
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intr_current_mask = intr_claimed_mask & ~intr_disabled_mask;
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irq_setmasks_nointr();
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}
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void
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stray_irqhandler(int irq)
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{
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panic("no handlers for IRQ %d (xint_mask = 0x%02x)\n", irq,
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CPLD_READ(IQ80310_XINT_MASK));
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}
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void *
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iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
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{
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irqhandler_t *ih, *ptr;
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u_int oldirqstate;
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int loop;
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_level = ipl;
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ih->ih_name = NULL;
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_flags = 0;
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ih->ih_num = irq;
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oldirqstate = disable_interrupts(I32_bit);
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/* Attach handler at top of chain */
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ih->ih_next = irqhandlers[irq];
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irqhandlers[irq] = ih;
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/* Update the IRQ masks. */
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ptr = irqhandlers[irq];
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if (ptr) {
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ipl = ptr->ih_level - 1;
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while (ptr) {
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if (ptr->ih_level - 1 < ipl)
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ipl = ptr->ih_level - 1;
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ptr = ptr->ih_next;
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}
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for (loop = 0; loop < IPL_LEVELS; ++loop) {
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if (ipl >= loop)
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irqmasks[loop] |= (1U << irq);
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else
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irqmasks[loop] &= ~(1U << irq);
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}
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}
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/* splimp > spltty */
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irqmasks[IPL_NET] &= irqmasks[IPL_TTY];
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/*
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* We now need to update the irqblock array. This array indicates
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* what other interrupts should be blocked when a given interrupt
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* is asserted. This basically emulates hardware interrupt
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* priorities e.g. by blocking all other IPL_BIO interrupts when
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* an IPL_BIO interrupt is asserted. For each interrupt, we find
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* the highest IPL and set the block mask to the interrupt mask
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* for that level.
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*/
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for (loop = 0; loop < NIRQS; ++loop) {
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ptr = irqhandlers[loop];
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if (ptr) {
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/* There is at least 1 handler so scan the chain */
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ipl = ptr->ih_level;
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while (ptr) {
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if (ptr->ih_level > ipl)
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ipl = ptr->ih_level;
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ptr = ptr->ih_next;
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}
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irqblock[loop] = ~irqmasks[ipl];
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} else {
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/* No handlers, so nothing else needs to be blocked. */
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irqblock[loop] = 0;
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}
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}
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enable_irq(irq);
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set_spl_masks();
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restore_interrupts(oldirqstate);
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return (ih);
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}
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void
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iq80310_intr_disestablish(void *cookie)
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{
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panic("iq80310_intr_disestablish");
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}
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