155 lines
5.4 KiB
C
155 lines
5.4 KiB
C
/* $NetBSD: ninjaata32reg.h,v 1.4 2011/02/21 02:32:00 itohy Exp $ */
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/*
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* Copyright (c) 2006 ITOH Yasufumi.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NJATA32REG_H_
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#define _NJATA32REG_H_
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/*
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* Workbit NinjaATA (32bit versions), IDE Controller with Busmastering PIO:
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* NinjaATA-32Bi PCMCIA/CardBus dual mode device ("DuoATA")
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* (CardBus mode only)
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* NPATA-32 CardBus device
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*/
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/*
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* CAVEAT
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* The names and the functions of the registers are probably incorrect
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* since no programming information is available in the public.
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*/
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#define NJATA32_REGSIZE 32 /* size of register set */
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#define NJATA32_MEMOFFSET_REG 0x860 /* offset of memory mapped register */
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#define NJATA32_REG_IRQ_STAT 0x00 /* len=1 RO */
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#define NJATA32_REG_IRQ_SELECT 0x01 /* len=1 WO */
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# define NJATA32_IRQ_XFER 0x01
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# define NJATA32_IRQ_DEV 0x04
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#define NJATA32_REG_IOBM 0x02 /* len=1 WO */
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# define NJATA32_IOBM_01 0x01
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# define NJATA32_IOBM_02 0x02
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# define NJATA32_IOBM_MMENBL 0x08
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# define NJATA32_IOBM_BURST 0x10
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# define NJATA32_IOBM_NO_BMSTART0 0x20
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# define NJATA32_IOBM_80 0x80
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# define NJATA32_IOBM_DEFAULT (NJATA32_IOBM_01 | NJATA32_IOBM_02 | \
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NJATA32_IOBM_BURST | NJATA32_IOBM_NO_BMSTART0 | NJATA32_IOBM_80)
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#define NJATA32_REG_AS 0x04 /* len=1 WO */
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# define NJATA32_AS_START 0x01 /* 0: PIO BM, 1: DMA BM */
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# define NJATA32_AS_WAIT0 0x00
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# define NJATA32_AS_WAIT1 0x04
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# define NJATA32_AS_WAIT2 0x08
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# define NJATA32_AS_WAIT3 0x0c
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# define NJATA32_AS_BUS_RESET 0x80
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#define NJATA32_REG_DMAADDR 0x08 /* len=4 R/W */
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#define NJATA32_REG_DMALENGTH 0x0c /* len=4 R/W */
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/*
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* WDC registers
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*/
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#define NJATA32_OFFSET_WDCREGS 0x10
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#define NJATA32_REG_WD_DATA 0x10 /* len=1/2/4 R/W */
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#define NJATA32_REG_WD_ERROR 0x11 /* len=1 RO */
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#define NJATA32_REG_WD_FEATURES 0x11 /* len=1 WO */
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#define NJATA32_REG_WD_SECCNT 0x12 /* len=1 R/W */
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#define NJATA32_REG_WD_IREASON 0x12 /* len=1 R/W (ATAPI) */
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#define NJATA32_REG_WD_SECTOR 0x13 /* len=1 R/W */
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#define NJATA32_REG_WD_LBA_LO 0x13 /* len=1 R/W */
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#define NJATA32_REG_WD_CYL_LO 0x14 /* len=1 R/W */
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#define NJATA32_REG_WD_LBA_MI 0x14 /* len=1 R/W */
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#define NJATA32_REG_WD_CYL_HI 0x15 /* len=1 R/W */
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#define NJATA32_REG_WD_LBA_HI 0x15 /* len=1 R/W */
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#define NJATA32_REG_WD_SDH 0x16 /* len=1 R/W */
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#define NJATA32_REG_WD_COMMAND 0x17 /* len=1 WO */
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#define NJATA32_REG_WD_STATUS 0x17 /* len=1 RO */
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#if 0 /* these registers seem to show the busmaster status */
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/* ? */
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#define NJATA32_REG_18 0x18 /* len=4 RO */
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/* ? */
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#define NJATA32_REG_1c 0x1c /* len=1 RO */
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#endif
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#define NJATA32_REG_BM 0x1d /* len=1 R/W */
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# define NJATA32_BM_EN 0x01
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# define NJATA32_BM_RD 0x02 /* 0: write, 1: read */
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# define NJATA32_BM_SG 0x04 /* 1: use scatter/gather tbl */
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# define NJATA32_BM_GO 0x08
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# define NJATA32_BM_WAIT0 0x00
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# define NJATA32_BM_WAIT1 0x10
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# define NJATA32_BM_WAIT2 0x20
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# define NJATA32_BM_WAIT3 0x30
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# define NJATA32_BM_WAIT_MASK 0x30
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# define NJATA32_BM_WAIT_SHIFT 4
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# define NJATA32_BM_DONE 0x80 /* ? */
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#define NJATA32_REG_WD_ALTSTATUS 0x1e /* len=1 R */
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#define NJATA32_REG_TIMING 0x1f /* len=1 W */
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/* timing values for PIO transfer */
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# define NJATA32_TIMING_PIO0 0xd6
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# define NJATA32_TIMING_PIO1 0x85
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# define NJATA32_TIMING_PIO2 0x44
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# define NJATA32_TIMING_PIO3 0x33
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# define NJATA32_TIMING_PIO4 0x13
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# define NJATA32_TIMING_PIO4_ 0x14 /* for timing tweak */
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# define NJATA32_TIMING_PIO4__ 0x24 /* for timing tweak */
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/* timing values for multiword DMA transfer */
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# define NJATA32_TIMING_DMA0 0x88
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# define NJATA32_TIMING_DMA1 0x23
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# define NJATA32_TIMING_DMA2 0x13
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/* timing values for obsolete singleword DMA transfer */
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# define NJATA32_TIMING_SMDMA0 0xff
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# define NJATA32_TIMING_SMDMA1 0x88
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# define NJATA32_TIMING_SMDMA2 0x44
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/*
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* DMA data structure
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*/
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/* scatter/gather transfer table entry (8 bytes) */
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struct njata32_sgtable {
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uint32_t sg_addr; /* transfer address (little endian) */
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uint32_t sg_len; /* transfer length (little endian) */
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#define NJATA32_SGT_ENDMARK 0x80000000
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#define NJATA32_SGT_MAXSEGLEN 0x10000
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};
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#define NJATA32_SGT_MAXENTRY 18
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/*
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* device specific constants
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*/
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#define NJATA32_MODE_MAX_DMA 2
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#define NJATA32_MODE_MAX_PIO 4
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#endif /* _NJATA32REG_H_ */
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