134 lines
3.9 KiB
C
134 lines
3.9 KiB
C
/* $NetBSD: atomic.h,v 1.9 2007/03/04 06:51:53 matt Exp $ */
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/*
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ATOMIC_H_
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#define _ARM_ATOMIC_H_
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#ifndef ATOMIC_SET_BIT_NONINLINE_REQUIRED
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#ifdef ATOMIC_SET_BIT_NOINLINE
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#define ATOMIC_SET_BIT_NONINLINE_REQUIRED
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#endif
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#endif /* ATOMIC_SET_BIT_NONINLINE_REQUIRED */
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#ifndef _LOCORE
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <arm/armreg.h> /* I32_bit */
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#ifdef ATOMIC_SET_BIT_NONINLINE_REQUIRED
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void atomic_set_bit( u_int *, u_int );
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void atomic_clear_bit( u_int *, u_int );
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bool atomic_cas(volatile uintptr_t *, uintptr_t, uintptr_t);
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#endif
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#ifdef __PROG32
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#define __with_interrupts_disabled(expr) \
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do { \
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u_int cpsr_save, tmp; \
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\
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__asm volatile( \
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"mrs %0, cpsr;" \
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"orr %1, %0, %2;" \
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"msr cpsr_all, %1;" \
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: "=r" (cpsr_save), "=r" (tmp) \
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: "I" (I32_bit) \
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: "cc" ); \
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(expr); \
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__asm volatile( \
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"msr cpsr_all, %0" \
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: /* no output */ \
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: "r" (cpsr_save) \
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: "cc" ); \
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} while(0)
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#else /* __PROG26 */
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#define __with_interrupts_disabled(expr) \
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do { \
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u_int r15_save, tmp; \
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\
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__asm volatile( \
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"mov %0, r15;" \
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"orr %1, %0, %2;" \
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"teqp %1, #0;" \
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: "=r" (r15_save), "=r" (tmp) \
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: "I" (R15_IRQ_DISABLE) \
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: "cc" ); \
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(expr); \
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__asm volatile( \
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"teqp %0, #0" \
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: /* no output */ \
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: "r" (r15_save) \
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: "cc" ); \
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} while(0)
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#endif /* __PROG26 */
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static __inline void
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inline_atomic_set_bit( u_int *address, u_int setmask )
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{
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__with_interrupts_disabled( *address |= setmask );
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}
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static __inline void
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inline_atomic_clear_bit( u_int *address, u_int clearmask )
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{
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__with_interrupts_disabled( *address &= ~clearmask );
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}
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static __inline bool
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inline_atomic_cas(volatile uintptr_t *cell, uintptr_t old, uintptr_t new)
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{
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bool rv;
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__with_interrupts_disabled(
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rv = (*cell == old ? ((*cell = new), true) : false) );
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return rv;
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}
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#if !defined(ATOMIC_SET_BIT_NOINLINE)
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#define atomic_set_bit(a,m) inline_atomic_set_bit(a,m)
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#define atomic_clear_bit(a,m) inline_atomic_clear_bit(a,m)
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#define atomic_cas(c,o,n) inline_atomic_cas(c,o,n)
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#endif
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#undef __with_interrupts_disabled
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#endif /* _KERNEL */
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#endif /* _LOCORE */
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#endif /* _ARM_ATOMIC_H_ */
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