246 lines
9.1 KiB
C
246 lines
9.1 KiB
C
/* $NetBSD: plumpcmciareg.h,v 1.4 2001/09/15 12:47:07 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* (CS3) */
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#define PLUM_PCMCIA_REGBASE 0x5000
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#define PLUM_PCMCIA_REGSIZE 0x1000
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/* (MCS0) */
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/* 1MByte */
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#define PLUM_PCMCIA_IOBASE1 0x00600000
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#define PLUM_PCMCIA_IOSIZE1 0x00100000
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/* 1MByte */
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#define PLUM_PCMCIA_IOBASE2 0x00700000
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#define PLUM_PCMCIA_IOSIZE2 0x00100000
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/* 8Mbyte */
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#define PLUM_PCMCIA_MEMBASE1 0x00800000
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#define PLUM_PCMCIA_MEMSIZE1 0x00800000
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/* 16MByte */
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#define PLUM_PCMCIA_MEMBASE2 0x01000000
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#define PLUM_PCMCIA_MEMSIZE2 0x01000000
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/* 32MByte */
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#define PLUM_PCMCIA_MEMBASE3 0x02000000
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#define PLUM_PCMCIA_MEMSIZE3 0x02000000
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/* (MCS1) */
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/* 64MByte */
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#define PLUM_PCMCIA_MEMBASE4 0x04000000
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#define PLUM_PCMCIA_MEMSIZE4 0x04000000
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/*
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* # of slots
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*/
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#define PLUMPCMCIA_NSLOTS 2
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/*
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* Control registers.
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*/
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#define PLUM_PCMCIA_REGSPACE_SLOT0 0
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#define PLUM_PCMCIA_REGSPACE_SLOT1 0x800
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#define PLUM_PCMCIA_REGSPACE_SIZE 0x800
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#define PLUM_PCMCIA_IDENT 0x000
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#define PLUM_PCMCIA_STATUS 0x004
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#define PLUM_PCMCIA_STATUS_BVD1 0x01
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#define PLUM_PCMCIA_STATUS_BVD2 0x02
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#define PLUM_PCMCIA_STATUS_CD1 0x04
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#define PLUM_PCMCIA_STATUS_CD2 0x08
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#define PLUM_PCMCIA_STATUS_WRITEPROTECT 0x10
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/* really READY/!BUSY */
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#define PLUM_PCMCIA_STATUS_READY 0x20
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#define PLUM_PCMCIA_STATUS_PWROK 0x40
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#define PLUM_PCMCIA_PWRCTRL 0x008
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/* output enable */
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#define PLUM_PCMCIA_PWRCTRL_OE 0x80
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#define PLUM_PCMCIA_PWRCTRL_DISABLE_RESETDRV 0x40
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#define PLUM_PCMCIA_PWRCTRL_AUTOSWITCH_ENABLE 0x20
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#define PLUM_PCMCIA_PWRCTRL_PWR_ENABLE 0x10
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#define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT1 0x08
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#define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT0 0x04
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#define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT1 0x02
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#define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT0 0x01
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#define PLUM_PCMCIA_GENCTRL 0x00c
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/* active low (zero) */
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#define PLUM_PCMCIA_GENCTRL_RESET 0x40
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#define PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK 0x20
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#define PLUM_PCMCIA_GENCTRL_CARDTYPE_IO 0x20
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#define PLUM_PCMCIA_GENCTRL_CARDTYPE_MEM 0x00
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#define PLUM_PCMCIA_CSCINT_STAT 0x010
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#define PLUM_PCMCIA_CSCINT 0x014
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#define PLUM_PCMCIA_CSCINT_BATTERY_DEAD 0x01
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#define PLUM_PCMCIA_CSCINT_BATTERY_WARNING 0x02
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#define PLUM_PCMCIA_CSCINT_READY 0x04
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#define PLUM_PCMCIA_CSCINT_CARD_DETECT 0x08
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#define PLUM_PCMCIA_WINEN 0x018
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#define PLUM_PCMCIA_WINEN_IO1 0x00000080
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#define PLUM_PCMCIA_WINEN_IO0 0x00000040
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#define PLUM_PCMCIA_WINEN_MEM4 0x00000010
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#define PLUM_PCMCIA_WINEN_MEM3 0x00000008
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#define PLUM_PCMCIA_WINEN_MEM2 0x00000004
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#define PLUM_PCMCIA_WINEN_MEM1 0x00000002
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#define PLUM_PCMCIA_WINEN_MEM0 0x00000001
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#define PLUM_PCMCIA_WINEN_MEM(x) (1 << (x))
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#define PLUM_PCMCIA_MEM_WINS 5
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#define PLUM_PCMCIA_MEM_SHIFT 12
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#define PLUM_PCMCIA_MEM_PAGESIZE (1<<PLUM_PCMCIA_MEM_SHIFT)
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#define PLUM_PCMCIA_IO_WINS 2
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#define PLUM_PCMCIA_IOWINCTRL 0x01c
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#define PLUM_PCMCIA_IOWINCTRL_WINMASK 0x0000000f
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#define PLUM_PCMCIA_IOWINCTRL_WIN0SHIFT 0
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#define PLUM_PCMCIA_IOWINCTRL_WIN1SHIFT 4
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#define PLUM_PCMCIA_IOWINCTRL_DATASIZE16 0x00000001
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#define PLUM_PCMCIA_IOWINCTRL_IOCS16SRC 0x00000002
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#define PLUM_PCMCIA_IOWINCTRL_ZEROWAIT 0x00000004
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#define PLUM_PCMCIA_IOWINCTRL_WAITSTATE 0x00000008
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#define PLUM_PCMCIA_IOWIN0STARTADDR 0x020
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#define PLUM_PCMCIA_IOWIN1STARTADDR 0x030
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#define PLUM_PCMCIA_IOWINSTARTADDR(x) \
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((x) * 0x10 + PLUM_PCMCIA_IOWIN0STARTADDR)
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#define PLUM_PCMCIA_IOWIN0STOPADDR 0x024
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#define PLUM_PCMCIA_IOWIN1STOPADDR 0x034
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#define PLUM_PCMCIA_IOWINSTOPADDR(x) \
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((x) * 0x10 + PLUM_PCMCIA_IOWIN0STOPADDR)
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#define PLUM_PCMCIA_IOWIN0ADDRCTRL 0x028
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#define PLUM_PCMCIA_IOWIN1ADDRCTRL 0x038
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#define PLUM_PCMCIA_IOWINADDRCTRL(x) \
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((x) * 0x10 + PLUM_PCMCIA_IOWIN0ADDRCTRL)
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#define PLUM_PCMCIA_IOWINADDRCTRL_AREA1 0x00000000
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#define PLUM_PCMCIA_IOWINADDRCTRL_AREA2 0x00000001
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#define PLUM_PCMCIA_MEMWIN0STARTADDR 0x040
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#define PLUM_PCMCIA_MEMWIN1STARTADDR 0x060
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#define PLUM_PCMCIA_MEMWIN2STARTADDR 0x080
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#define PLUM_PCMCIA_MEMWIN3STARTADDR 0x0a0
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#define PLUM_PCMCIA_MEMWIN4STARTADDR 0x0c0
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#define PLUM_PCMCIA_MEMWINSTARTADDR(x) \
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((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STARTADDR)
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#define PLUM_PCMCIA_MEMWIN0STOPADDR 0x044
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#define PLUM_PCMCIA_MEMWIN1STOPADDR 0x064
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#define PLUM_PCMCIA_MEMWIN2STOPADDR 0x084
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#define PLUM_PCMCIA_MEMWIN3STOPADDR 0x0a4
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#define PLUM_PCMCIA_MEMWIN4STOPADDR 0x0c4
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#define PLUM_PCMCIA_MEMWINSTOPADDR(x) \
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((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STOPADDR)
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#define PLUM_PCMCIA_MEMWIN0OFSADDR 0x048
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#define PLUM_PCMCIA_MEMWIN1OFSADDR 0x068
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#define PLUM_PCMCIA_MEMWIN2OFSADDR 0x088
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#define PLUM_PCMCIA_MEMWIN3OFSADDR 0x0a8
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#define PLUM_PCMCIA_MEMWIN4OFSADDR 0x0c8
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#define PLUM_PCMCIA_MEMWINOFSADDR(x) \
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((x) * 0x20 + PLUM_PCMCIA_MEMWIN0OFSADDR)
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#define PLUM_PCMCIA_MEMWIN0CTRL 0x04c
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#define PLUM_PCMCIA_MEMWIN1CTRL 0x06c
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#define PLUM_PCMCIA_MEMWIN2CTRL 0x08c
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#define PLUM_PCMCIA_MEMWIN3CTRL 0x0ac
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#define PLUM_PCMCIA_MEMWIN4CTRL 0x0cc
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#define PLUM_PCMCIA_MEMWINCTRL(x) \
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((x) * 0x20 + PLUM_PCMCIA_MEMWIN0CTRL)
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT 24
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_MASK 0x3
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#define PLUM_PCMCIA_MEMWINCTRL_MAP(cr) \
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(((cr) >> PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) & \
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PLUM_PCMCIA_MEMWINCTRL_MAP_MASK)
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_SET(cr, val) \
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((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) & \
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(PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT)))
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_CLEAR(cr) \
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((cr) &= ~(PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT))
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA1 0x0
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA2 0x1
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA3 0x2
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#define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA4 0x3
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#define PLUM_PCMCIA_MEMWINCTRL_WRPROTECT 0x00800000
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#define PLUM_PCMCIA_MEMWINCTRL_REGACTIVE 0x00400000
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#define PLUM_PCMCIA_MEMWINCTRL_DATASIZE16 0x00000080
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#define PLUM_PCMCIA_MEMWINCTRL_ZERO_WS 0x00000040
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT 14
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK 0x3
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING(cr) \
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(((cr) >> PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) & \
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PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK)
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_SET(cr, val) \
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((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) & \
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(PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK << \
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PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT)))
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_STD 0x0
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_1WAIT 0x1
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_2WAIT 0x2
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#define PLUM_PCMCIA_MEMWINCTRL_TIMING_3WAIT 0x3
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#define PLUM_PCMCIA_MEMWINCTRL_DATASIZE_16BIT 0x00000080 /* else 8bit */
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#define PLUM_PCMCIA_MEMWINCTRL_ZEROWS 0x00000040
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#define PLUM_PCMCIA_GENCTRL2 0x058
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#define PLUM_PCMCIA_GENCTRL2_VCC5V 0x000000c0
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#define PLUM_PCMCIA_GENCTRL2_VCC3V 0x00000080
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#define PLUM_PCMCIA_GLOBALCTRL 0x078
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#define PLUM_PCMCIA_GLOBALCTRL_EXPLICIT_WB_CSC_INT 0x04
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#define PLUM_PCMCIA_TIMING 0x0ec
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#define PLUM_PCMCIA_FUNCCTRL 0x0f8
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#define PLUM_PCMCIA_FUNCCTRL_3VSUPPORT 0x00000001
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#define PLUM_PCMCIA_FUNCCTRL_VSSEN 0x00000002
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#define PLUM_PCMCIA_SPECIALMODE 0x0fc
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#define PLUM_PCMCIA_SLOTCTRL 0x100
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#define PLUM_PCMCIA_SLOTCTRL_ENABLE 0x00000080
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#define PLUM_PCMCIA_BUFOFF 0x104
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#define PLUM_PCMCIA_CARDDETECTMODE 0x108
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#define PLUM_PCMCIA_CARDPWRCTRL 0x10c
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#define PLUM_PCMCIA_CARDPWRCTRL_OFF 1
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#define PLUM_PCMCIA_CARDPWRCTRL_ON 0
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