204183c0fa
NULL for root PCI busses. For busses behind a bridge, it points to a persistent copy of the bridge's pcitag_t. This can be very useful for machine-dependent PCI bus enumeration code. * Implement a machine-dependent pci_enumerate_bus() for sparc64 which uses OFW device nodes to enumerate the bus. When a PCI bus that is behind a bridge is attached, pci_attach_hook() allocates a new PCI chipset tag for the new bus and sets it's "curnode" to the OFW node of the bridge. This is used as a starting point when enumerating that bus. Root busses get the OFW node of the host bridge (psycho). * Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
227 lines
5.7 KiB
C
227 lines
5.7 KiB
C
/* $NetBSD: gt.c,v 1.2 2002/05/16 01:01:36 thorpej Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/pci/pcivar.h>
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#include <evbmips/malta/maltareg.h>
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#include <evbmips/malta/maltavar.h>
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#include <evbmips/malta/dev/gtreg.h>
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#include <evbmips/malta/dev/gtvar.h>
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#include "pci.h"
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/*
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* Galileo systems (so far) are always single-processor, so this is sufficient.
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*/
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#define PCI_CONF_LOCK(s) (s) = splhigh()
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#define PCI_CONF_UNLOCK(s) splx((s))
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static void gt_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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static int gt_bus_maxdevs(void *, int);
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static pcitag_t gt_make_tag(void *, int, int, int);
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static void gt_decompose_tag(void *, pcitag_t, int *, int *, int *);
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static pcireg_t gt_conf_read(void *, pcitag_t, int);
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static void gt_conf_write(void *, pcitag_t, int, pcireg_t);
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void
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gt_pci_init(pci_chipset_tag_t pc, struct gt_config *mcp)
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{
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pc->pc_conf_v = mcp;
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pc->pc_attach_hook = gt_attach_hook;
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pc->pc_bus_maxdevs = gt_bus_maxdevs;
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pc->pc_make_tag = gt_make_tag;
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pc->pc_decompose_tag = gt_decompose_tag;
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pc->pc_conf_read = gt_conf_read;
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pc->pc_conf_write = gt_conf_write;
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}
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static void
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gt_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* Nothing to do... */
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}
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static int gt_match(struct device *, struct cfdata *, void *);
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static void gt_attach(struct device *, struct device *, void *);
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static int gt_print(void *aux, const char *pnp);
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struct cfattach gt_ca = {
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sizeof(struct device), gt_match, gt_attach
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};
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static int
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gt_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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return 1;
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}
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static void
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gt_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct malta_config *mcp = &malta_configuration;
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struct pcibus_attach_args pba;
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printf("\n");
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#if NPCI > 0
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pba.pba_busname = "pci";
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pba.pba_bus = 0;
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pba.pba_bridgetag = NULL;
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pba.pba_iot = &mcp->mc_iot;
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pba.pba_memt = &mcp->mc_memt;
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pba.pba_dmat = &mcp->mc_pci_dmat; /* pci_bus_dma_tag */
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//pba.pba_dmat = &pci_bus_dma_tag;
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pba.pba_pc = &mcp->mc_pc;
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config_found(self, &pba, gt_print);
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#endif
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return;
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}
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static int
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gt_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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/* XXX */
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return 0;
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}
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static int
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gt_bus_maxdevs(void *v, int busno)
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{
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/* The galileo has problems accessing device 31. */
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if (busno == 0)
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return (31);
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return (32);
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}
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static pcitag_t
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gt_make_tag(void *v, int b, int d, int f)
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{
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return ((b << 16) | (d << 11) | (f << 8));
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}
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static void
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gt_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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static pcireg_t
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gt_conf_read(void *v, pcitag_t tag, int offset)
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{
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pcireg_t data;
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int bus, dev, func, s;
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gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
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/* The galileo has problems accessing device 31. */
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if (bus == 0 && dev == 31)
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return ((pcireg_t) -1);
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/* XXX: no support for bus > 0 yet */
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if (bus > 0)
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return ((pcireg_t) -1);
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PCI_CONF_LOCK(s);
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/* Clear cause register bits. */
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GT_REGVAL(GT_INTR_CAUSE) = 0;
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GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
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data = GT_REGVAL(GT_PCI0_CFG_DATA);
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/* Check for master abort. */
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if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
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data = (pcireg_t) -1;
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PCI_CONF_UNLOCK(s);
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return (data);
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}
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static void
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gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
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{
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int bus, dev, func, s;
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gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
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/* The galileo has problems accessing device 31. */
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if (bus == 0 && dev == 31)
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return;
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/* XXX: no support for bus > 0 yet */
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if (bus > 0)
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return;
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PCI_CONF_LOCK(s);
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/* Clear cause register bits. */
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GT_REGVAL(GT_INTR_CAUSE) = 0;
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GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
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GT_REGVAL(GT_PCI0_CFG_DATA) = data;
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PCI_CONF_UNLOCK(s);
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}
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