204183c0fa
NULL for root PCI busses. For busses behind a bridge, it points to a persistent copy of the bridge's pcitag_t. This can be very useful for machine-dependent PCI bus enumeration code. * Implement a machine-dependent pci_enumerate_bus() for sparc64 which uses OFW device nodes to enumerate the bus. When a PCI bus that is behind a bridge is attached, pci_attach_hook() allocates a new PCI chipset tag for the new bus and sets it's "curnode" to the OFW node of the bridge. This is used as a starting point when enumerating that bus. Root busses get the OFW node of the host bridge (psycho). * Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
715 lines
17 KiB
C
715 lines
17 KiB
C
/* $NetBSD: pci_machdep.c,v 1.35 2002/05/16 01:01:34 thorpej Exp $ */
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/*
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* Copyright (c) 1996 Leo Weppelman. All rights reserved.
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* Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_mbtype.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#define _ATARI_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <uvm/uvm_extern.h>
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#include <machine/cpu.h>
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#include <machine/iomap.h>
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#include <machine/mfp.h>
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#include <atari/atari/device.h>
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#include <atari/pci/pci_vga.h>
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/*
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* Sizes of pci memory and I/O area.
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*/
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#define PCI_MEM_END 0x10000000 /* 256 MByte */
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#define PCI_IO_END 0x10000000 /* 256 MByte */
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/*
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* We preserve some space at the begin of the pci area for 32BIT_1M
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* devices and standard vga.
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*/
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#define PCI_MEM_START 0x00100000 /* 1 MByte */
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#define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only
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I/O addresses up to 0xffff) */
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/*
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* PCI memory and IO should be aligned acording to this masks
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*/
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#define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00
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#define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000
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/*
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* Convert a PCI 'device' number to a slot number.
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*/
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#define DEV2SLOT(dev) (3 - dev)
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/*
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* Struct to hold the memory and I/O datas of the pci devices
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*/
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struct pci_memreg {
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LIST_ENTRY(pci_memreg) link;
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int dev;
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pcitag_t tag;
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pcireg_t reg, address, mask;
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u_int32_t size;
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u_int32_t csr;
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};
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typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG;
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/*
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* Entry points for PCI DMA. Use only the 'standard' functions.
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*/
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int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t,
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bus_size_t, int, bus_dmamap_t *));
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struct atari_bus_dma_tag pci_bus_dma_tag = {
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0,
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#if defined(_ATARIHW_)
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0x80000000, /* On the Hades, CPU memory starts here PCI-wise */
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#else
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0,
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#endif
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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_bus_dmamap_sync,
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};
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int pcibusprint __P((void *auxp, const char *));
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int pcibusmatch __P((struct device *, struct cfdata *, void *));
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void pcibusattach __P((struct device *, struct device *, void *));
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static void enable_pci_devices __P((void));
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static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem));
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static int overlap_pci_areas __P((struct pci_memreg *p,
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struct pci_memreg *self, u_int addr, u_int size, u_int what));
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struct cfattach pcibus_ca = {
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sizeof(struct device), pcibusmatch, pcibusattach
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};
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/*
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* We need some static storage to probe pci-busses for VGA cards during
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* early console init.
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*/
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static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */
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int
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pcibusmatch(pdp, cfp, auxp)
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struct device *pdp;
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struct cfdata *cfp;
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void *auxp;
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{
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static int nmatched = 0;
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if (strcmp((char *)auxp, "pcibus"))
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return (0); /* Wrong number... */
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if(atari_realconfig == 0)
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return (1);
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if (machineid & (ATARI_HADES|ATARI_MILAN)) {
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/*
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* Both Hades and Milan have only one pci bus
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*/
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if (nmatched)
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return (0);
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nmatched++;
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return (1);
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}
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return (0);
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}
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void
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pcibusattach(pdp, dp, auxp)
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struct device *pdp, *dp;
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void *auxp;
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{
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struct pcibus_attach_args pba;
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pba.pba_busname = "pci";
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pba.pba_pc = NULL;
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pba.pba_bus = 0;
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pba.pba_bridgetag = NULL;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pba.pba_dmat = &pci_bus_dma_tag;
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pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]);
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pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]);
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if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) {
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printf("leb_alloc_bus_space_tag failed!\n");
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return;
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}
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pba.pba_iot->base = PCI_IO_PHYS;
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pba.pba_memt->base = PCI_MEM_PHYS;
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if (dp == NULL) {
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/*
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* Scan the bus for a VGA-card that we support. If we
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* find one, try to initialize it to a 'standard' text
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* mode (80x25).
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*/
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check_for_vga(pba.pba_iot, pba.pba_memt);
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return;
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}
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enable_pci_devices();
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#if defined(_ATARIHW_)
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MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */
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#endif
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printf("\n");
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config_found(dp, &pba, pcibusprint);
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}
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int
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pcibusprint(auxp, name)
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void *auxp;
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const char *name;
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{
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if(name == NULL)
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return(UNCONF);
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return(QUIET);
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}
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void
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pci_attach_hook(parent, self, pba)
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struct device *parent, *self;
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struct pcibus_attach_args *pba;
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{
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}
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/*
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* Initialize the PCI-bus. The Atari-BIOS does not do this, so....
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* We only disable all devices here. Memory and I/O enabling is done
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* later at pcibusattach.
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*/
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void
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init_pci_bus()
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{
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pci_chipset_tag_t pc = NULL; /* XXX */
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pcitag_t tag;
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pcireg_t csr;
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int device, id, maxndevs;
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tag = 0;
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id = 0;
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maxndevs = pci_bus_maxdevs(pc, 0);
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for (device = 0; device < maxndevs; device++) {
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tag = pci_make_tag(pc, 0, device, 0);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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if (id == 0 || id == 0xffffffff)
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continue;
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
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csr &= ~PCI_COMMAND_MASTER_ENABLE;
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
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}
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}
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/*
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* insert a new element in an existing list that the ID's (size in struct
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* pci_memreg) are sorted.
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*/
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static void
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insert_into_list(head, elem)
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PCI_MEMREG *head;
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struct pci_memreg *elem;
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{
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struct pci_memreg *p, *q;
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p = LIST_FIRST(head);
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q = NULL;
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for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link));
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if (q == NULL) {
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LIST_INSERT_HEAD(head, elem, link);
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} else {
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LIST_INSERT_AFTER(q, elem, link);
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}
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}
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/*
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* Test if a new selected area overlaps with an already (probably preselected)
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* pci area.
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*/
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static int
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overlap_pci_areas(p, self, addr, size, what)
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struct pci_memreg *p, *self;
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u_int addr, size, what;
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{
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struct pci_memreg *q;
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if (p == NULL)
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return 0;
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q = p;
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while (q != NULL) {
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if ((q != self) && (q->csr & what)) {
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if ((addr >= q->address) && (addr < (q->address + q->size))) {
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#ifdef DEBUG_PCI_MACHDEP
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printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
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self->dev, self->reg, q->dev, q->reg);
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#endif
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return 1;
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}
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if ((q->address >= addr) && (q->address < (addr + size))) {
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#ifdef DEBUG_PCI_MACHDEP
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printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
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self->dev, self->reg, q->dev, q->reg);
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#endif
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return 1;
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}
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}
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q = LIST_NEXT(q, link);
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}
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return 0;
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}
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/*
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* Enable memory and I/O on pci devices. Care about already enabled devices
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* (probabaly by the console driver).
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*
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* The idea behind the following code is:
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* We build a by sizes sorted list of the requirements of the different
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* pci devices. After that we choose the start addresses of that areas
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* in such a way that they are placed as closed as possible together.
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*/
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static void
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enable_pci_devices()
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{
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PCI_MEMREG memlist;
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PCI_MEMREG iolist;
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struct pci_memreg *p, *q;
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int dev, reg, id, class;
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pcitag_t tag;
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pcireg_t csr, address, mask;
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pci_chipset_tag_t pc;
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int sizecnt, membase_1m;
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pc = 0;
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csr = 0;
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tag = 0;
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LIST_INIT(&memlist);
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LIST_INIT(&iolist);
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/*
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* first step: go through all devices and gather memory and I/O
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* sizes
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*/
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for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) {
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tag = pci_make_tag(pc, 0, dev, 0);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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if (id == 0 || id == 0xffffffff)
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continue;
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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/*
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* special case: if a display card is found and memory is enabled
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* preserve 128k at 0xa0000 as vga memory.
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* XXX: if a display card is found without being enabled, leave
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* it alone! You will usually only create conflicts by enabeling
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* it.
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*/
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class = pci_conf_read(pc, tag, PCI_CLASS_REG);
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switch (PCI_CLASS(class)) {
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case PCI_CLASS_PREHISTORIC:
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case PCI_CLASS_DISPLAY:
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if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
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p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
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M_TEMP, M_WAITOK);
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memset(p, '\0', sizeof(struct pci_memreg));
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p->dev = dev;
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p->csr = csr;
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p->tag = tag;
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p->reg = 0; /* there is no register about this */
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p->size = 0x20000; /* 128kByte */
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p->mask = 0xfffe0000;
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p->address = 0xa0000;
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insert_into_list(&memlist, p);
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}
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else continue;
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}
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for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
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address = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, 0xffffffff);
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mask = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, address);
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if (mask == 0)
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continue; /* Register unused */
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p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
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M_TEMP, M_WAITOK);
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memset(p, '\0', sizeof(struct pci_memreg));
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p->dev = dev;
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p->csr = csr;
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p->tag = tag;
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p->reg = reg;
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p->mask = mask;
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p->address = 0;
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if (mask & PCI_MAPREG_TYPE_IO) {
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p->size = PCI_MAPREG_IO_SIZE(mask);
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/*
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* Align IO if necessary
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*/
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if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) {
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p->mask = PCI_MACHDEP_IO_ALIGN_MASK;
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p->size = PCI_MAPREG_IO_SIZE(p->mask);
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}
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/*
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* if I/O is already enabled (probably by the console driver)
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* save the address in order to take care about it later.
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*/
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if (csr & PCI_COMMAND_IO_ENABLE)
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p->address = address;
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insert_into_list(&iolist, p);
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} else {
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p->size = PCI_MAPREG_MEM_SIZE(mask);
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/*
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* Align memory if necessary
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*/
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if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) {
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p->mask = PCI_MACHDEP_MEM_ALIGN_MASK;
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p->size = PCI_MAPREG_MEM_SIZE(p->mask);
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}
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/*
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* if memory is already enabled (probably by the console driver)
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* save the address in order to take care about it later.
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*/
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if (csr & PCI_COMMAND_MEM_ENABLE)
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p->address = address;
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insert_into_list(&memlist, p);
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if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT)
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reg++;
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}
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}
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#if defined(_ATARIHW_)
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/*
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* Both interrupt pin & line are set to the device (== slot)
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* number. This makes sense on the atari Hades because the
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* individual slots are hard-wired to a specific MFP-pin.
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*/
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csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT);
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csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT);
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pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr);
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#else
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/*
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* On the Milan, we accept the BIOS's choice.
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*/
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#endif
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}
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/*
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* second step: calculate the memory and I/O adresses beginning from
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* PCI_MEM_START and PCI_IO_START. Care about already mapped areas.
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*
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* begin with memory list
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*/
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address = PCI_MEM_START;
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sizecnt = 0;
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membase_1m = 0;
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p = LIST_FIRST(&memlist);
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while (p != NULL) {
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if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) {
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if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) {
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if (p->size > membase_1m)
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membase_1m = p->size;
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do {
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p->address = membase_1m;
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membase_1m += p->size;
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} while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
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p->size, PCI_COMMAND_MEM_ENABLE));
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if (membase_1m > 0x00100000) {
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/*
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* Should we panic here?
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*/
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printf("\npcibus0: dev %d reg %d: memory not configured",
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p->dev, p->reg);
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p->reg = 0;
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}
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} else {
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if (sizecnt && (p->size > sizecnt))
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|
sizecnt = ((p->size + sizecnt) & p->mask) &
|
|
PCI_MAPREG_MEM_ADDR_MASK;
|
|
if (sizecnt > address) {
|
|
address = sizecnt;
|
|
sizecnt = 0;
|
|
}
|
|
|
|
do {
|
|
p->address = address + sizecnt;
|
|
sizecnt += p->size;
|
|
} while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
|
|
p->size, PCI_COMMAND_MEM_ENABLE));
|
|
|
|
if ((address + sizecnt) > PCI_MEM_END) {
|
|
/*
|
|
* Should we panic here?
|
|
*/
|
|
printf("\npcibus0: dev %d reg %d: memory not configured",
|
|
p->dev, p->reg);
|
|
p->reg = 0;
|
|
}
|
|
}
|
|
if (p->reg > 0) {
|
|
pci_conf_write(pc, p->tag, p->reg, p->address);
|
|
csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
|
|
csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
|
|
pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
|
|
p->csr = csr;
|
|
}
|
|
}
|
|
p = LIST_NEXT(p, link);
|
|
}
|
|
|
|
/*
|
|
* now the I/O list
|
|
*/
|
|
|
|
address = PCI_IO_START;
|
|
sizecnt = 0;
|
|
p = LIST_FIRST(&iolist);
|
|
while (p != NULL) {
|
|
if (!(p->csr & PCI_COMMAND_IO_ENABLE)) {
|
|
|
|
if (sizecnt && (p->size > sizecnt))
|
|
sizecnt = ((p->size + sizecnt) & p->mask) &
|
|
PCI_MAPREG_IO_ADDR_MASK;
|
|
if (sizecnt > address) {
|
|
address = sizecnt;
|
|
sizecnt = 0;
|
|
}
|
|
|
|
do {
|
|
p->address = address + sizecnt;
|
|
sizecnt += p->size;
|
|
} while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address,
|
|
p->size, PCI_COMMAND_IO_ENABLE));
|
|
|
|
if ((address + sizecnt) > PCI_IO_END) {
|
|
/*
|
|
* Should we panic here?
|
|
*/
|
|
printf("\npcibus0: dev %d reg %d: io not configured",
|
|
p->dev, p->reg);
|
|
} else {
|
|
pci_conf_write(pc, p->tag, p->reg, p->address);
|
|
csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
|
|
csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
|
|
pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
|
|
p->csr = csr;
|
|
}
|
|
}
|
|
p = LIST_NEXT(p, link);
|
|
}
|
|
|
|
#ifdef DEBUG_PCI_MACHDEP
|
|
printf("\nI/O List:\n");
|
|
p = LIST_FIRST(&iolist);
|
|
|
|
while (p != NULL) {
|
|
printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
|
|
p->reg, p->size, p->address);
|
|
p = LIST_NEXT(p, link);
|
|
}
|
|
printf("\nMemlist:");
|
|
p = LIST_FIRST(&memlist);
|
|
|
|
while (p != NULL) {
|
|
printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
|
|
p->reg, p->size, p->address);
|
|
p = LIST_NEXT(p, link);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Free the lists
|
|
*/
|
|
p = LIST_FIRST(&iolist);
|
|
while (p != NULL) {
|
|
q = p;
|
|
LIST_REMOVE(q, link);
|
|
free(p, M_WAITOK);
|
|
p = LIST_FIRST(&iolist);
|
|
}
|
|
p = LIST_FIRST(&memlist);
|
|
while (p != NULL) {
|
|
q = p;
|
|
LIST_REMOVE(q, link);
|
|
free(p, M_WAITOK);
|
|
p = LIST_FIRST(&memlist);
|
|
}
|
|
}
|
|
|
|
pcitag_t
|
|
pci_make_tag(pc, bus, device, function)
|
|
pci_chipset_tag_t pc;
|
|
int bus, device, function;
|
|
{
|
|
return ((bus << 16) | (device << 11) | (function << 8));
|
|
}
|
|
|
|
void
|
|
pci_decompose_tag(pc, tag, bp, dp, fp)
|
|
pci_chipset_tag_t pc;
|
|
pcitag_t tag;
|
|
int *bp, *dp, *fp;
|
|
{
|
|
|
|
if (bp != NULL)
|
|
*bp = (tag >> 16) & 0xff;
|
|
if (dp != NULL)
|
|
*dp = (tag >> 11) & 0x1f;
|
|
if (fp != NULL)
|
|
*fp = (tag >> 8) & 0x7;
|
|
}
|
|
|
|
int
|
|
pci_intr_map(pa, ihp)
|
|
struct pci_attach_args *pa;
|
|
pci_intr_handle_t *ihp;
|
|
{
|
|
int line = pa->pa_intrline;
|
|
|
|
#if defined(_MILANHW_)
|
|
/*
|
|
* On the Hades, the 'pin' info is useless.
|
|
*/
|
|
{
|
|
int pin = pa->pa_intrpin;
|
|
|
|
if (pin == 0) {
|
|
/* No IRQ used. */
|
|
goto bad;
|
|
}
|
|
if (pin > PCI_INTERRUPT_PIN_MAX) {
|
|
printf("pci_intr_map: bad interrupt pin %d\n", pin);
|
|
goto bad;
|
|
}
|
|
}
|
|
#endif /* _MILANHW_ */
|
|
|
|
/*
|
|
* According to the PCI-spec, 255 means `unknown' or `no connection'.
|
|
* Interpret this as 'no interrupt assigned'.
|
|
*/
|
|
if (line == 255)
|
|
goto bad;
|
|
|
|
/*
|
|
* Values are pretty useless on the Hades since all interrupt
|
|
* lines for a card are tied together and hardwired to a
|
|
* specific TT-MFP I/O port.
|
|
* On the Milan, they are tied to the ICU.
|
|
*/
|
|
#if defined(_MILANHW_)
|
|
if (line >= 16) {
|
|
printf("pci_intr_map: bad interrupt line %d\n", line);
|
|
goto bad;
|
|
}
|
|
if (line == 2) {
|
|
printf("pci_intr_map: changed line 2 to line 9\n");
|
|
line = 9;
|
|
}
|
|
/* Assume line == 0 means unassigned */
|
|
if (line == 0)
|
|
goto bad;
|
|
#endif
|
|
*ihp = line;
|
|
return 0;
|
|
|
|
bad:
|
|
*ihp = -1;
|
|
return 1;
|
|
}
|
|
|
|
const char *
|
|
pci_intr_string(pc, ih)
|
|
pci_chipset_tag_t pc;
|
|
pci_intr_handle_t ih;
|
|
{
|
|
static char irqstr[8]; /* 4 + 2 + NULL + sanity */
|
|
|
|
if (ih == -1)
|
|
panic("pci_intr_string: bogus handle 0x%x\n", ih);
|
|
|
|
sprintf(irqstr, "irq %d", ih);
|
|
return (irqstr);
|
|
|
|
}
|
|
|
|
const struct evcnt *
|
|
pci_intr_evcnt(pc, ih)
|
|
pci_chipset_tag_t pc;
|
|
pci_intr_handle_t ih;
|
|
{
|
|
|
|
/* XXX for now, no evcnt parent reported */
|
|
return NULL;
|
|
}
|