51 lines
2.2 KiB
C
51 lines
2.2 KiB
C
/* $NetBSD: vrc4172pmureg.h,v 1.2 2001/04/13 08:11:44 itojun Exp $ */
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/*
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* Copyright (c) 2000 SATO Kazumi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vrc4172 PMU unit register definition
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*/
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#define VRC2_PMU_SYSCLKCTRL 0x00
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#define VRC2_PMU_IRST 0x20 /* internal reset */
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#define VRC2_PMU_OSCDIS 0x10 /* OSC disable */
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#define VRC2_PMU_CKO48 0x01 /* CKO48 enable */
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#define VRC2_PMU_1284CTRL 0x02
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#define VRC2_PMU_1284EN 0x04 /* 1284 enable */
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#define VRC2_PMU_1284RST 0x02 /* 1284 reset (>= 1us) */
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#define VRC2_PMU_1284CLKDIS 0x01 /* 1284 clock disanle */
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#define VRC2_PMU_16550CTRL 0x04
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#define VRC2_PMU_16550RST 0x02 /* 16550 reset (>= 200ms) */
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#define VRC2_PMU_16550CLKDIS 0x01 /* 16550 clock disable */
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#define VRC2_PMU_USBCTL 0x0c
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#define VRC2_PMU_USBCLKDIS 0x01 /* USB clock disable */
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#define VRC2_PMU_PS2PWMCTL 0x0e
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#define VRC2_PMU_PWMCLKDIS 0x10 /* PWM clock disable */
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#define VRC2_PMU_PS2RST 0x02 /* PS2 reset */
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#define VRC2_PMU_PS2CLKDIS 0x01 /* PS2 clock disable */
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/* end */
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