158 lines
7.3 KiB
C
158 lines
7.3 KiB
C
/* $NetBSD: iommu.h,v 1.5 1998/01/22 22:07:45 gwr Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jeremy Cooper.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Structure and definition of descriptors used in the I/O Mapper.
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*/
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#ifndef _SUN3X_IOMMU_H
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#define _SUN3X_IOMMU_H
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/* The I/O Mapper is a special type of MMU in the sun3x architecture
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* (and supposedly in the sun4m as well) that translates an address used by a
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* device during a DMA transfer into an address on the internal system bus.
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* In other words, it is an MMU that stands between devices wishing to do DMA
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* transfers and main memory. In this description, the address issued by a
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* DMA device is called a ``DVMA address'', while the address as it is
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* translated and output from the I/O mapper is called a ``system bus address''
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* (sometimes known as a ``physical address'').
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*
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* The DVMA address space in the sun3x architecture is 24 bits wide, in
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* contrast with the system bus address space, which is 32. The mapping of a
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* DVMA address to a system bus address is accomplished by dividing the DVMA
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* address space into 2048 8K pages. Each DVMA page is then mapped to a
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* system bus address using a mapping described by a page descriptor entry
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* within the I/O Mapper. This 2048 entry, page descriptor table is located
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* at physical address 0x60000000 in the sun3x architecture and can be
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* manipulated by the CPU with normal read and write cycles.
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*
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* In addition to describing an address mapping, a page descriptor entry also
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* indicates whether the DVMA page is read-only, should be inhibited from
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* caching by system caches, and whether or not DMA write transfers to it will
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* be completed in 16 byte aligned blocks. (This last item is used for cache
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* optimization in sun3x systems with special DMA caches.)
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*
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* Since not every DMA device is capable of addressing all 24 bits of the
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* DVMA address space, each is wired so that the end of its address space is
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* always flush against the end of the DVMA address space. That is, a device
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* with a 16 bit address space (and hence an address space size of 64k) is
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* wired such that it accesses the top 64k of DVMA space.
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*/
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/** I/O MAPPER Page Descriptor Entry
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* 31 16
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | PAGE PHYSICAL ADDRESS BITS (31..13) |
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* +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+
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* | | UNUSED | CI| BX| M | U | WP| DT |
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* +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+
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* 15 0
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*
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* <CI> CACHE INHIBIT - When set, prevents instructions and data from the
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* page from being cached in any system cache.
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* <BX> FULL BLOCK XFER - When set, acts as an indicator to the caching system
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* that all DMA transfers to this DVMA page will fill
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* complete I/O cache blocks, eliminating the need for
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* the cache block to be filled from main memory first
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* before the DMA write can proceed to it.
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* <M> MODIFIED - Set when the cpu has modified (written to) the
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* physical page.
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* <U> USED - Set when the cpu has accessed the physical page.
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* <WP> WRITE PROTECT - When set, prevents all DMA devices from writing to
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* the page.
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* <DT> DESCRIPTOR TYPE - One of the following values:
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* 00 = Invalid page
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* 01 = Valid page
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* 1x = Invalid code for a page descriptor.
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*/
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struct iommu_pde_struct {
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union {
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struct {
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u_int pa:19; /* Physical Address */
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u_int unused:6; /* Unused bits */
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u_int ci:1; /* Cache Inhibit */
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u_int bx:1; /* Full Block Xfer */
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u_int m:1; /* Modified bit */
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u_int u:1; /* Used bit */
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u_int wp:1; /* Write Protect bit */
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u_int dt:2; /* Descriptor type */
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/* Masks for the above fields. */
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#define IOMMU_PDE_PA 0xFFFFE000
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#define IOMMU_PDE_UNUSED 0x00001F80
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#define IOMMU_PDE_CI 0x00000040
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#define IOMMU_PDE_BX 0x00000020
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#define IOMMU_PDE_M 0x00000010
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#define IOMMU_PDE_USED 0x00000008
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#define IOMMU_PDE_WP 0x00000004
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#define IOMMU_PDE_DT 0x00000003
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/* The descriptor types */
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#define IOMMU_PDE_DT_INVALID 0x00000000 /* Invalid page */
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#define IOMMU_PDE_DT_VALID 0x00000001 /* Valid page */
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} stc;
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u_int32_t raw; /* For unstructured access to the above */
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} addr;
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};
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typedef struct iommu_pde_struct iommu_pde_t;
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/* Constants */
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#define IOMMU_PAGE_SIZE (8 * 1024)
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#define IOMMU_PAGE_SHIFT 13
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/* Useful macros */
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#define IOMMU_PA_PDE(pde) ((pde).addr.raw & IOMMU_PDE_PA)
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#define IOMMU_VALID_DT(pde) ((pde).addr.raw & IOMMU_PDE_DT) /* X1 */
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#define IOMMU_BTOP(pa) (((u_int) pa) >> IOMMU_PAGE_SHIFT)
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/* X1: This macro will incorrectly report the validity for entries which
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* contain codes that are invalid. (Do not confuse this with the code for
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* 'invalid entry', which means that the descriptor is properly formed, but
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* just not used.)
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*/
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/* Constants for the I/O mapper as used in the sun3x */
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#define IOMMU_NENT 2048 /* Number of PTEs in the map */
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/* Similarly, the virtual address mask. */
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#define IOMMU_VA_MASK 0xFFffff /* 16MB */
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#ifdef _KERNEL
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/* Interfaces for manipulating the I/O mapper */
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void iommu_enter __P((u_int32_t va, u_int32_t pa));
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void iommu_remove __P((u_int32_t va, u_int32_t len));
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#endif /* _KERNEL */
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#endif /* _SUN3X_IOMMU_H */
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